Simulation Results: uart

 
04/05/2026 19:40:26 DVSim: v1.33.1 sha: c46226f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.71 %
  • code
  • 96.77 %
  • assert
  • 96.25 %
  • func
  • 55.12 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.90 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 12.220s 5763.478us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.610s 43.896us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.580s 49.130us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.780s 59.584us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.780s 52.251us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.840s 32.004us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.580s 49.130us 1 1 100.00
uart_csr_aliasing 0.780s 52.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 23.960s 66793.429us 1 1 100.00
parity 2 2 100.00
uart_smoke 12.220s 5763.478us 1 1 100.00
uart_tx_rx 23.960s 66793.429us 1 1 100.00
parity_error 2 2 100.00
uart_intr 18.630s 54199.374us 1 1 100.00
uart_rx_parity_err 216.820s 89914.839us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 23.960s 66793.429us 1 1 100.00
uart_intr 18.630s 54199.374us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 27.210s 71208.457us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 89.520s 184943.308us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 9.940s 128422.027us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 18.630s 54199.374us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 18.630s 54199.374us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 18.630s 54199.374us 1 1 100.00
perf 1 1 100.00
uart_perf 140.330s 14906.338us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.330s 4237.642us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.330s 4237.642us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 17.770s 18223.089us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.230s 1083.091us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 11.680s 6704.126us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.670s 6926.040us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 431.650s 103258.698us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 57.410s 42249.643us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.630s 55.941us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.650s 25.200us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.760s 185.667us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.760s 185.667us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.610s 43.896us 1 1 100.00
uart_csr_rw 0.580s 49.130us 1 1 100.00
uart_csr_aliasing 0.780s 52.251us 1 1 100.00
uart_same_csr_outstanding 1.060s 27.013us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.610s 43.896us 1 1 100.00
uart_csr_rw 0.580s 49.130us 1 1 100.00
uart_csr_aliasing 0.780s 52.251us 1 1 100.00
uart_same_csr_outstanding 1.060s 27.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.850s 62.194us 1 1 100.00
uart_tl_intg_err 1.010s 65.439us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.010s 65.439us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 11.390s 1243.169us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *
uart_noise_filter 34911362544615525377050981225569306932734434530794013164135449821642873076100 76
UVM_ERROR @ 18172046171 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 18173067037 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 18174087903 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 18176129635 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0