Simulation Results: aes/masked

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.45 %
  • code
  • 95.19 %
  • assert
  • 98.43 %
  • func
  • 65.74 %
  • block
  • 95.88 %
  • line
  • 97.52 %
  • branch
  • 89.82 %
  • toggle
  • 97.96 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
89.47%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 163.119us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 103.478us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 53.943us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 76.865us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 911.471us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 81.482us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 106.726us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 76.865us 1 1 100.00
aes_csr_aliasing 2.000s 81.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 103.478us 1 1 100.00
aes_config_error 3.000s 83.071us 1 1 100.00
aes_stress 6.000s 105.156us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 103.478us 1 1 100.00
aes_config_error 3.000s 83.071us 1 1 100.00
aes_stress 6.000s 105.156us 1 1 100.00
back2back 2 2 100.00
aes_stress 6.000s 105.156us 1 1 100.00
aes_b2b 9.000s 439.583us 1 1 100.00
backpressure 1 1 100.00
aes_stress 6.000s 105.156us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 4.000s 103.478us 1 1 100.00
aes_config_error 3.000s 83.071us 1 1 100.00
aes_stress 6.000s 105.156us 1 1 100.00
aes_alert_reset 28.000s 10012.022us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 151.436us 1 1 100.00
aes_config_error 3.000s 83.071us 1 1 100.00
aes_alert_reset 28.000s 10012.022us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 162.991us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 1144.484us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 10.000s 549.957us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 28.000s 10012.022us 0 1 0.00
stress 1 1 100.00
aes_stress 6.000s 105.156us 1 1 100.00
sideload 2 2 100.00
aes_stress 6.000s 105.156us 1 1 100.00
aes_sideload 4.000s 84.472us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 336.006us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 51.000s 11935.945us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 7.000s 556.850us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 81.696us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 376.820us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 376.820us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 53.943us 1 1 100.00
aes_csr_rw 2.000s 76.865us 1 1 100.00
aes_csr_aliasing 2.000s 81.482us 1 1 100.00
aes_same_csr_outstanding 1.000s 130.767us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 53.943us 1 1 100.00
aes_csr_rw 2.000s 76.865us 1 1 100.00
aes_csr_aliasing 2.000s 81.482us 1 1 100.00
aes_same_csr_outstanding 1.000s 130.767us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 16.000s 743.250us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 17.000s 10045.780us 0 1 0.00
aes_control_fi 2.000s 50.008us 1 1 100.00
aes_cipher_fi 2.000s 60.213us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 277.707us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 277.707us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 277.707us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 277.707us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 325.616us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1470.329us 1 1 100.00
aes_tl_intg_err 2.000s 139.227us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 139.227us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 28.000s 10012.022us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 277.707us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 277.707us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 4.000s 103.478us 1 1 100.00
aes_stress 6.000s 105.156us 1 1 100.00
aes_alert_reset 28.000s 10012.022us 0 1 0.00
aes_core_fi 3.000s 102.533us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 7.000s 556.850us 1 1 100.00
aes_config_error 3.000s 83.071us 1 1 100.00
aes_stress 6.000s 105.156us 1 1 100.00
aes_core_fi 3.000s 102.533us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 277.707us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 75.421us 1 1 100.00
aes_stress 6.000s 105.156us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 6.000s 105.156us 1 1 100.00
aes_sideload 4.000s 84.472us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 75.421us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 75.421us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 75.421us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 75.421us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 75.421us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 6.000s 105.156us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 6.000s 105.156us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 17.000s 10045.780us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 17.000s 10045.780us 0 1 0.00
aes_control_fi 2.000s 50.008us 1 1 100.00
aes_cipher_fi 2.000s 60.213us 1 1 100.00
aes_ctr_fi 3.000s 127.188us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 17.000s 10045.780us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 17.000s 10045.780us 0 1 0.00
aes_control_fi 2.000s 50.008us 1 1 100.00
aes_cipher_fi 2.000s 60.213us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 60.213us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 17.000s 10045.780us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 17.000s 10045.780us 0 1 0.00
aes_control_fi 2.000s 50.008us 1 1 100.00
aes_ctr_fi 3.000s 127.188us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 17.000s 10045.780us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 17.000s 10045.780us 0 1 0.00
aes_control_fi 2.000s 50.008us 1 1 100.00
aes_cipher_fi 2.000s 60.213us 1 1 100.00
aes_ctr_fi 3.000s 127.188us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 28.000s 10012.022us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 17.000s 10045.780us 0 1 0.00
aes_control_fi 2.000s 50.008us 1 1 100.00
aes_cipher_fi 2.000s 60.213us 1 1 100.00
aes_ctr_fi 3.000s 127.188us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 17.000s 10045.780us 0 1 0.00
aes_control_fi 2.000s 50.008us 1 1 100.00
aes_cipher_fi 2.000s 60.213us 1 1 100.00
aes_ctr_fi 3.000s 127.188us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 17.000s 10045.780us 0 1 0.00
aes_control_fi 2.000s 50.008us 1 1 100.00
aes_ctr_fi 3.000s 127.188us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 17.000s 10045.780us 0 1 0.00
aes_ghash_fi 1.000s 69.797us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 17.000s 10045.780us 0 1 0.00
aes_control_fi 2.000s 50.008us 1 1 100.00
aes_cipher_fi 2.000s 60.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 4.000s 364.856us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred! 2 test runs
aes_alert_reset 87694165797931430394549378324630703255417111120705826687892553400849687494008 1336
UVM_INFO @ 10012022296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 52081917617415043573442825569705627667162982976238203711610451406020048767469 94329
UVM_INFO @ 11935944883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred! 1 test run
aes_fi 56843859528943342740843074855833582849069422785614376315912299981706334457653 3872
UVM_INFO @ 10045779960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 7781978727246857273956249389955035143459818216636814903396365086828163733928 296
UVM_INFO @ 364856197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---