Simulation Results: aes/unmasked

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.68 %
  • code
  • 91.52 %
  • assert
  • 97.75 %
  • func
  • 67.76 %
  • block
  • 91.21 %
  • line
  • 93.42 %
  • branch
  • 83.89 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
89.47%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 53.879us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 176.533us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 63.857us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 93.833us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 863.543us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 229.934us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 73.413us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 93.833us 1 1 100.00
aes_csr_aliasing 2.000s 229.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 176.533us 1 1 100.00
aes_config_error 2.000s 110.242us 1 1 100.00
aes_stress 3.000s 79.765us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 176.533us 1 1 100.00
aes_config_error 2.000s 110.242us 1 1 100.00
aes_stress 3.000s 79.765us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 79.765us 1 1 100.00
aes_b2b 6.000s 1047.127us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 79.765us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 176.533us 1 1 100.00
aes_config_error 2.000s 110.242us 1 1 100.00
aes_stress 3.000s 79.765us 1 1 100.00
aes_alert_reset 30.000s 10003.920us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 1.000s 56.518us 1 1 100.00
aes_config_error 2.000s 110.242us 1 1 100.00
aes_alert_reset 30.000s 10003.920us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 104.982us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 707.366us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 468.571us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 30.000s 10003.920us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 79.765us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 79.765us 1 1 100.00
aes_sideload 3.000s 199.478us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 68.003us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 19.000s 10009.947us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 87.456us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 93.377us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 179.276us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 179.276us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 63.857us 1 1 100.00
aes_csr_rw 1.000s 93.833us 1 1 100.00
aes_csr_aliasing 2.000s 229.934us 1 1 100.00
aes_same_csr_outstanding 2.000s 229.197us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 63.857us 1 1 100.00
aes_csr_rw 1.000s 93.833us 1 1 100.00
aes_csr_aliasing 2.000s 229.934us 1 1 100.00
aes_same_csr_outstanding 2.000s 229.197us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 87.988us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 23.000s 10019.784us 0 1 0.00
aes_control_fi 2.000s 45.288us 1 1 100.00
aes_cipher_fi 2.000s 48.429us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 114.264us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 114.264us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 114.264us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 114.264us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 354.048us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 908.058us 1 1 100.00
aes_tl_intg_err 2.000s 326.303us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 326.303us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 30.000s 10003.920us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 114.264us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 114.264us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 176.533us 1 1 100.00
aes_stress 3.000s 79.765us 1 1 100.00
aes_alert_reset 30.000s 10003.920us 0 1 0.00
aes_core_fi 2.000s 68.970us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 87.456us 1 1 100.00
aes_config_error 2.000s 110.242us 1 1 100.00
aes_stress 3.000s 79.765us 1 1 100.00
aes_core_fi 2.000s 68.970us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 114.264us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 73.945us 1 1 100.00
aes_stress 3.000s 79.765us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 79.765us 1 1 100.00
aes_sideload 3.000s 199.478us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 73.945us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 73.945us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 73.945us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 73.945us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 73.945us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 79.765us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 79.765us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 23.000s 10019.784us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 23.000s 10019.784us 0 1 0.00
aes_control_fi 2.000s 45.288us 1 1 100.00
aes_cipher_fi 2.000s 48.429us 1 1 100.00
aes_ctr_fi 1.000s 65.484us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 23.000s 10019.784us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 23.000s 10019.784us 0 1 0.00
aes_control_fi 2.000s 45.288us 1 1 100.00
aes_cipher_fi 2.000s 48.429us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 48.429us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 23.000s 10019.784us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 23.000s 10019.784us 0 1 0.00
aes_control_fi 2.000s 45.288us 1 1 100.00
aes_ctr_fi 1.000s 65.484us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 23.000s 10019.784us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 23.000s 10019.784us 0 1 0.00
aes_control_fi 2.000s 45.288us 1 1 100.00
aes_cipher_fi 2.000s 48.429us 1 1 100.00
aes_ctr_fi 1.000s 65.484us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 30.000s 10003.920us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 23.000s 10019.784us 0 1 0.00
aes_control_fi 2.000s 45.288us 1 1 100.00
aes_cipher_fi 2.000s 48.429us 1 1 100.00
aes_ctr_fi 1.000s 65.484us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 23.000s 10019.784us 0 1 0.00
aes_control_fi 2.000s 45.288us 1 1 100.00
aes_cipher_fi 2.000s 48.429us 1 1 100.00
aes_ctr_fi 1.000s 65.484us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 23.000s 10019.784us 0 1 0.00
aes_control_fi 2.000s 45.288us 1 1 100.00
aes_ctr_fi 1.000s 65.484us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 23.000s 10019.784us 0 1 0.00
aes_ghash_fi 2.000s 66.788us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 23.000s 10019.784us 0 1 0.00
aes_control_fi 2.000s 45.288us 1 1 100.00
aes_cipher_fi 2.000s 48.429us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 7.000s 4764.007us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred! 2 test runs
aes_alert_reset 18547439710155474180843887528080300589589590563226328594509499434326779642359 374
UVM_INFO @ 10003919767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 107819933530324282806619186193668150695665620205327895256266153152066883879649 960
UVM_INFO @ 10009946655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred! 1 test run
aes_fi 61381988655773243002998079300715232914030384417760414374484564535472620281584 815
UVM_INFO @ 10019783771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 21727110571617255467609201354014274049970292364179855969982040232624963661570 550
UVM_INFO @ 4764007343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---