Simulation Results: alert_handler

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.12 %
  • code
  • 91.14 %
  • assert
  • 98.11 %
  • func
  • 78.10 %
  • line
  • 99.71 %
  • branch
  • 97.69 %
  • cond
  • 90.52 %
  • toggle
  • 91.99 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 50.470s 1263.117us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.060s 226.957us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 7.760s 142.067us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 319.370s 25825.083us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 121.510s 8661.304us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.970s 209.635us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 7.760s 142.067us 1 1 100.00
alert_handler_csr_aliasing 121.510s 8661.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 161.020s 3675.509us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 4.300s 70.317us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1101.930s 22430.536us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 41.970s 2950.213us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 50.470s 1263.117us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 8.580s 991.511us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 39.460s 3474.501us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 37.560s 6385.807us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1194.510s 34381.594us 1 1 100.00
alert_handler_lpg_stub_clk 916.800s 28064.630us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2331.180s 57670.848us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 8.640s 426.528us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.740s 56.518us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.200s 10.864us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 13.460s 490.173us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 13.460s 490.173us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.060s 226.957us 1 1 100.00
alert_handler_csr_rw 7.760s 142.067us 1 1 100.00
alert_handler_csr_aliasing 121.510s 8661.304us 1 1 100.00
alert_handler_same_csr_outstanding 15.710s 2172.748us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.060s 226.957us 1 1 100.00
alert_handler_csr_rw 7.760s 142.067us 1 1 100.00
alert_handler_csr_aliasing 121.510s 8661.304us 1 1 100.00
alert_handler_same_csr_outstanding 15.710s 2172.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 85.460s 3689.361us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 85.460s 3689.361us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 85.460s 3689.361us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 85.460s 3689.361us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 506.810s 9559.894us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 17.530s 854.507us 1 1 100.00
alert_handler_tl_intg_err 35.390s 775.914us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 35.390s 775.914us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 85.460s 3689.361us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 50.470s 1263.117us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 50.470s 1263.117us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 50.470s 1263.117us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 50.470s 1263.117us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 41.970s 2950.213us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1194.510s 34381.594us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 41.970s 2950.213us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1101.930s 22430.536us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1101.930s 22430.536us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.530s 854.507us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.530s 854.507us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.530s 854.507us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.530s 854.507us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 17.530s 854.507us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.530s 854.507us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.530s 854.507us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.530s 854.507us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 17.530s 854.507us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 94.850s 8217.164us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. 1 test run
alert_handler_ping_timeout 54651423506995542964960422608141628413910779243528884923080765053520251639215 80
UVM_INFO @ 6385807454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 1397891301702854241010924927210339851933219883179313209451722200661388783022 130
UVM_INFO @ 8217163740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---