Simulation Results: clkmgr

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.41 %
  • code
  • 76.20 %
  • assert
  • 93.18 %
  • func
  • 65.85 %
  • line
  • 90.37 %
  • branch
  • 93.54 %
  • cond
  • 85.73 %
  • toggle
  • 98.87 %
  • FSM
  • 12.50 %
Validation stages
V1
33.33%
V2
53.85%
V2S
37.50%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.920s 30.127us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.860s 28.683us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.620s 2.620us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.080s 37.947us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.850s 14.166us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.140s 43.712us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.620s 2.620us 0 1 0.00
clkmgr_csr_aliasing 0.850s 14.166us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.570s 118.254us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.980s 39.646us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.730s 24.134us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.920s 30.127us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.700s 10.372us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.590s 3.514us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.700s 10.372us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.720s 4.676us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.040s 37.884us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.160s 25.540us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.160s 25.540us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.860s 28.683us 1 1 100.00
clkmgr_csr_rw 0.620s 2.620us 0 1 0.00
clkmgr_csr_aliasing 0.850s 14.166us 0 1 0.00
clkmgr_same_csr_outstanding 0.730s 8.050us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.860s 28.683us 1 1 100.00
clkmgr_csr_rw 0.620s 2.620us 0 1 0.00
clkmgr_csr_aliasing 0.850s 14.166us 0 1 0.00
clkmgr_same_csr_outstanding 0.730s 8.050us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 3.960s 385.299us 1 1 100.00
clkmgr_tl_intg_err 0.640s 3.678us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 0.980s 33.216us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 0.980s 33.216us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 0.980s 33.216us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 0.980s 33.216us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.150s 61.139us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.640s 3.678us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.700s 10.372us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.590s 3.514us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 0.980s 33.216us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.960s 164.866us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.620s 2.620us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.960s 385.299us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.620s 2.620us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.620s 2.620us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.960s 385.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 0.780s 21.145us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.890s 10.725us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency 106170488644106548320342225353754586870496373161389786964385401946686096356659 76
UVM_INFO @ 10372394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 37148694637557665146028311877379383464485616001678150598422904186692931684071 78
UVM_INFO @ 10724564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 7628701018199712764278747982352360593608748535700184065988272877250049560613 76
UVM_INFO @ 4675666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 1440445398566483711666742256334918672074599868760757244750489185209860504242 75
UVM_INFO @ 61138693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 83687725311504396367140950239755465040781325523245594317589208503930032812122 78
UVM_INFO @ 3678449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 71402954856724898584416858410344313881060979232201554842006762835090756262504 76
UVM_INFO @ 14165614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_csr_rw 27626537835274005509583354904374753509434095923424340132583497405485039844212 75
UVM_INFO @ 2619825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 93411365623787964937754017468246976381128703599351670237535779346372810699503 82
UVM_INFO @ 43712484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency_timeout 27385219685052383771633134292793811374071682918042615191986384375318871880461 78
UVM_INFO @ 3514233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 47336604534609205321098460149804327944076619586443953256209999453183853439334 75
UVM_INFO @ 37946696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 85222504883746732030321701856569620236092348700792778364886555965237468213099 75
UVM_INFO @ 8049702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---