Simulation Results: csrng

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.63 %
  • code
  • 92.18 %
  • assert
  • 91.92 %
  • func
  • 78.78 %
  • block
  • 96.85 %
  • line
  • 97.62 %
  • branch
  • 92.08 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 36.993us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 58.684us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 13.160us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 12.000s 712.643us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 31.342us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 51.748us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 13.160us 1 1 100.00
csrng_csr_aliasing 3.000s 31.342us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
alerts 1 1 100.00
csrng_alert 7.000s 98.744us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 65.853us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 65.853us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 529.000s 28308.634us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 16.194us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 56.539us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 250.353us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 250.353us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 58.684us 1 1 100.00
csrng_csr_rw 2.000s 13.160us 1 1 100.00
csrng_csr_aliasing 3.000s 31.342us 1 1 100.00
csrng_same_csr_outstanding 2.000s 15.895us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 58.684us 1 1 100.00
csrng_csr_rw 2.000s 13.160us 1 1 100.00
csrng_csr_aliasing 3.000s 31.342us 1 1 100.00
csrng_same_csr_outstanding 2.000s 15.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 64.142us 1 1 100.00
csrng_tl_intg_err 3.000s 212.239us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 12.581us 1 1 100.00
csrng_csr_rw 2.000s 13.160us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 7.000s 98.744us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 529.000s 28308.634us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
csrng_sec_cm 3.000s 64.142us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
csrng_sec_cm 3.000s 64.142us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
csrng_sec_cm 3.000s 64.142us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
csrng_sec_cm 3.000s 64.142us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
csrng_sec_cm 3.000s 64.142us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 7.000s 98.744us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 529.000s 28308.634us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 7.000s 98.744us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 212.239us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
csrng_sec_cm 3.000s 64.142us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
csrng_sec_cm 3.000s 64.142us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 8.000s 391.363us 1 1 100.00
csrng_err 2.000s 21.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 10802.143s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 62463313738313398948980675106856270633906876906598527699855337419740737432910 130
UVM_INFO @ 65853495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 3525916658346333753459147324851748795634812383596814064969121726036768041376 None