Simulation Results: dma

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 80.59 %
  • code
  • 91.12 %
  • assert
  • 95.97 %
  • func
  • 54.69 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 88.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 617.134us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 604.728us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 283.098us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 78.019us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 96.101us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 9.000s 1247.514us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 156.014us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 51.309us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 96.101us 1 1 100.00
dma_csr_aliasing 5.000s 156.014us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 36.000s 11569.275us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 651.000s 112616.258us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 88.000s 8129.855us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 88.000s 8129.855us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 651.000s 112616.258us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 145.000s 11810.619us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 88.000s 8129.855us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 6.000s 355.583us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 78.000s 24351.932us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 121.977us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 42.205us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 479.942us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 479.942us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 78.019us 1 1 100.00
dma_csr_rw 1.000s 96.101us 1 1 100.00
dma_csr_aliasing 5.000s 156.014us 1 1 100.00
dma_same_csr_outstanding 2.000s 40.942us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 78.019us 1 1 100.00
dma_csr_rw 1.000s 96.101us 1 1 100.00
dma_csr_aliasing 5.000s 156.014us 1 1 100.00
dma_same_csr_outstanding 2.000s 40.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 11.000s 177.703us 1 1 100.00
dma_generic_stress 145.000s 11810.619us 1 1 100.00
dma_handshake_stress 88.000s 8129.855us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 665.118us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 4.000s 221.228us 1 1 100.00
dma_sec_cm 1.000s 17.632us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 59.000s 12457.913us 1 1 100.00
dma_longer_transfer 3.000s 216.931us 1 1 100.00
dma_stress_all_with_rand_reset 2.000s 732.045us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 7706997783781670005324988426698415410802207557459504979400291094285240267658 94
UVM_INFO @ 732044813ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---