Simulation Results: edn/edn0

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.39 %
  • code
  • 82.96 %
  • assert
  • 95.66 %
  • func
  • 80.56 %
  • line
  • 97.88 %
  • branch
  • 92.19 %
  • cond
  • 87.93 %
  • toggle
  • 85.21 %
  • FSM
  • 51.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 18.413us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.950s 19.503us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.930s 34.616us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.750s 443.305us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.370s 33.975us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.260s 78.081us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.930s 34.616us 1 1 100.00
edn_csr_aliasing 1.370s 33.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 4.270s 723.318us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 4.270s 723.318us 1 1 100.00
genbits 1 1 100.00
edn_genbits 4.270s 723.318us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.920s 26.076us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.120s 79.252us 1 1 100.00
errs 1 1 100.00
edn_err 0.860s 18.323us 1 1 100.00
disable 2 2 100.00
edn_disable 0.810s 13.273us 1 1 100.00
edn_disable_auto_req_mode 1.500s 46.379us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.680s 1061.669us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.780s 26.102us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.960s 87.326us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.660s 216.247us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.660s 216.247us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.950s 19.503us 1 1 100.00
edn_csr_rw 0.930s 34.616us 1 1 100.00
edn_csr_aliasing 1.370s 33.975us 1 1 100.00
edn_same_csr_outstanding 0.910s 81.127us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.950s 19.503us 1 1 100.00
edn_csr_rw 0.930s 34.616us 1 1 100.00
edn_csr_aliasing 1.370s 33.975us 1 1 100.00
edn_same_csr_outstanding 0.910s 81.127us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.410s 956.360us 1 1 100.00
edn_tl_intg_err 1.840s 111.479us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.890s 46.474us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.120s 79.252us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.410s 956.360us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.410s 956.360us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.410s 956.360us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.410s 956.360us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.120s 79.252us 1 1 100.00
edn_sec_cm 6.410s 956.360us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.120s 79.252us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.840s 111.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 95.660s 11067.514us 1 1 100.00