Simulation Results: edn/edn1

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.97 %
  • code
  • 84.79 %
  • assert
  • 97.14 %
  • func
  • 78.99 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 89.69 %
  • toggle
  • 95.06 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.840s 36.012us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.890s 43.348us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 92.979us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.510s 133.642us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.320s 52.192us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.980s 195.889us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 92.979us 1 1 100.00
edn_csr_aliasing 1.320s 52.192us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.950s 65.108us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.950s 65.108us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.950s 65.108us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 34.693us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.040s 86.695us 1 1 100.00
errs 1 1 100.00
edn_err 1.050s 29.015us 1 1 100.00
disable 2 2 100.00
edn_disable 0.860s 52.062us 1 1 100.00
edn_disable_auto_req_mode 0.910s 30.122us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.240s 238.229us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.850s 22.747us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.900s 12.861us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.400s 408.603us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.400s 408.603us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.890s 43.348us 1 1 100.00
edn_csr_rw 0.790s 92.979us 1 1 100.00
edn_csr_aliasing 1.320s 52.192us 1 1 100.00
edn_same_csr_outstanding 1.070s 130.667us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.890s 43.348us 1 1 100.00
edn_csr_rw 0.790s 92.979us 1 1 100.00
edn_csr_aliasing 1.320s 52.192us 1 1 100.00
edn_same_csr_outstanding 1.070s 130.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.190s 282.095us 1 1 100.00
edn_tl_intg_err 1.540s 88.558us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.980s 60.616us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.040s 86.695us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.190s 282.095us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.190s 282.095us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.190s 282.095us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.190s 282.095us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.040s 86.695us 1 1 100.00
edn_sec_cm 2.190s 282.095us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.040s 86.695us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.540s 88.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 47.330s 4180.508us 1 1 100.00