Simulation Results: hmac

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.68 %
  • code
  • 97.80 %
  • assert
  • 96.70 %
  • func
  • 44.55 %
  • line
  • 99.64 %
  • branch
  • 99.34 %
  • cond
  • 95.90 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 0.950s 516.870us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.840s 51.244us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.910s 283.087us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.230s 866.708us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.580s 180.003us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 83.360s 22709.398us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.910s 283.087us 1 1 100.00
hmac_csr_aliasing 2.580s 180.003us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 36.590s 3186.177us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 24.010s 912.647us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.670s 167.905us 1 1 100.00
hmac_test_sha384_vectors 20.840s 856.285us 1 1 100.00
hmac_test_sha512_vectors 440.760s 24074.152us 1 1 100.00
hmac_test_hmac256_vectors 10.090s 4059.450us 1 1 100.00
hmac_test_hmac384_vectors 10.680s 351.728us 1 1 100.00
hmac_test_hmac512_vectors 11.010s 1012.798us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 6.550s 852.858us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 210.210s 1919.839us 1 1 100.00
error 1 1 100.00
hmac_error 8.010s 1198.093us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 91.580s 10605.770us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 0.950s 516.870us 1 1 100.00
hmac_long_msg 36.590s 3186.177us 1 1 100.00
hmac_back_pressure 24.010s 912.647us 1 1 100.00
hmac_datapath_stress 210.210s 1919.839us 1 1 100.00
hmac_burst_wr 6.550s 852.858us 1 1 100.00
hmac_stress_all 147.530s 4277.728us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 0.950s 516.870us 1 1 100.00
hmac_long_msg 36.590s 3186.177us 1 1 100.00
hmac_back_pressure 24.010s 912.647us 1 1 100.00
hmac_datapath_stress 210.210s 1919.839us 1 1 100.00
hmac_wipe_secret 91.580s 10605.770us 1 1 100.00
hmac_test_sha256_vectors 8.670s 167.905us 1 1 100.00
hmac_test_sha384_vectors 20.840s 856.285us 1 1 100.00
hmac_test_sha512_vectors 440.760s 24074.152us 1 1 100.00
hmac_test_hmac256_vectors 10.090s 4059.450us 1 1 100.00
hmac_test_hmac384_vectors 10.680s 351.728us 1 1 100.00
hmac_test_hmac512_vectors 11.010s 1012.798us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 0.950s 516.870us 1 1 100.00
hmac_long_msg 36.590s 3186.177us 1 1 100.00
hmac_back_pressure 24.010s 912.647us 1 1 100.00
hmac_datapath_stress 210.210s 1919.839us 1 1 100.00
hmac_burst_wr 6.550s 852.858us 1 1 100.00
hmac_error 8.010s 1198.093us 1 1 100.00
hmac_wipe_secret 91.580s 10605.770us 1 1 100.00
hmac_test_sha256_vectors 8.670s 167.905us 1 1 100.00
hmac_test_sha384_vectors 20.840s 856.285us 1 1 100.00
hmac_test_sha512_vectors 440.760s 24074.152us 1 1 100.00
hmac_test_hmac256_vectors 10.090s 4059.450us 1 1 100.00
hmac_test_hmac384_vectors 10.680s 351.728us 1 1 100.00
hmac_test_hmac512_vectors 11.010s 1012.798us 1 1 100.00
hmac_stress_all 147.530s 4277.728us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 147.530s 4277.728us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.640s 13.849us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.740s 17.341us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.180s 965.633us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.180s 965.633us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.840s 51.244us 1 1 100.00
hmac_csr_rw 0.910s 283.087us 1 1 100.00
hmac_csr_aliasing 2.580s 180.003us 1 1 100.00
hmac_same_csr_outstanding 1.050s 54.473us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.840s 51.244us 1 1 100.00
hmac_csr_rw 0.910s 283.087us 1 1 100.00
hmac_csr_aliasing 2.580s 180.003us 1 1 100.00
hmac_same_csr_outstanding 1.050s 54.473us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.940s 131.223us 1 1 100.00
hmac_tl_intg_err 3.770s 292.326us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.770s 292.326us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 0.950s 516.870us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.170s 188.452us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 45.490s 77724.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.040s 73.709us 1 1 100.00