Simulation Results

Simulation Results: i2c

05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.41 %

code
81.18 %

assert
96.19 %

func
78.86 %

line
96.35 %

branch
92.12 %

cond
84.52 %

toggle
89.45 %

FSM
43.45 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	11.190s	4334.072us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	8.910s	8009.974us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.820s	30.164us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.880s	46.182us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.170s	476.976us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.680s	45.833us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.850s	29.541us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.880s	46.182us	1	1	100.00
	i2c_csr_aliasing	1.680s	45.833us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.950s	27.481us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	71.140s	14534.986us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	94.820s	26469.527us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.830s	45.489us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	79.910s	5135.719us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	32.190s	3559.297us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.090s	72.684us	1	1	100.00
	i2c_host_fifo_fmt_empty	13.800s	807.328us	1	1	100.00
	i2c_host_fifo_reset_rx	7.300s	294.032us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	41.490s	4222.026us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	12.980s	1309.049us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.680s	279.965us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.280s	2076.029us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	63.190s	31515.820us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.450s	699.627us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	28.450s	1003.866us	1	1	100.00
	i2c_target_intr_smoke	2.520s	477.480us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.080s	138.077us	1	1	100.00
	i2c_target_fifo_reset_tx	1.230s	245.613us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	29.080s	38749.548us	1	1	100.00
	i2c_target_stress_rd	28.450s	1003.866us	1	1	100.00
	i2c_target_intr_stress_wr	94.600s	11621.639us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.690s	1282.490us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	13.360s	10012.773us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.640s	3778.839us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	6.390s	10053.082us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.390s	2343.071us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.940s	469.021us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	94.820s	26469.527us	1	1	100.00
	i2c_host_perf_precise	22.430s	2689.352us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	12.980s	1309.049us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.790s	92.785us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.210s	574.511us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.040s	506.167us	1	1	100.00
	i2c_target_nack_txstretch	1.120s	120.295us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	7.690s	559.737us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.550s	1103.012us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.770s	45.852us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.760s	50.436us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.020s	26.858us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.020s	26.858us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.820s	30.164us	1	1	100.00
	i2c_csr_rw	0.880s	46.182us	1	1	100.00
	i2c_csr_aliasing	1.680s	45.833us	1	1	100.00
	i2c_same_csr_outstanding	1.210s	39.843us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.820s	30.164us	1	1	100.00
	i2c_csr_rw	0.880s	46.182us	1	1	100.00
	i2c_csr_aliasing	1.680s	45.833us	1	1	100.00
	i2c_same_csr_outstanding	1.210s	39.843us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.270s	123.539us	1	1	100.00
	i2c_sec_cm	1.110s	161.563us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.270s	123.539us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	8.060s	186.781us	1
target_error_intr				1
	i2c_target_unexp_stop	1.090s	327.552us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	11.800s	1042.242us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	3552183317041407890731150860841269196130840984583282719938000864504281114138	96	UVM_INFO @ 27480717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	112561579335295498427010371179509491512989321369183738586678760627514592835657	141	UVM_INFO @ 14534985740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	106971257340786873608643286839674944573210712762711406241847394775319460438739	85	UVM_INFO @ 186781028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	69224719367839029799282327084460485747764139286221560555541598333717084762710	90	UVM_INFO @ 1042241961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	88346573828095536671138266829526515866333801649619040279099262121034159715239	84	UVM_INFO @ 2076029016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!				1 test run
	i2c_target_stretch	36318278614740643681213625659630139023086245069998371602646144765370212062161	78	UVM_INFO @ 10012772731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	80084001287280207705776265325086796193046279379139109429604862475133424446054	83	UVM_INFO @ 327552140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	102819315292871910461883972688834472177260474050063356919522266069614726870652	79	UVM_INFO @ 10053082184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	107011044523335631845678359081732200965775595839506252864581587743704804444567	83	UVM_INFO @ 120294868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---