Simulation Results: kmac/unmasked

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.49 %
  • code
  • 88.08 %
  • assert
  • 97.75 %
  • func
  • 91.63 %
  • line
  • 97.14 %
  • branch
  • 94.46 %
  • cond
  • 91.79 %
  • toggle
  • 100.00 %
  • FSM
  • 57.02 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 9.760s 3540.938us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.160s 103.261us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.910s 78.474us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 7.950s 727.464us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.860s 402.217us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.460s 72.124us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.910s 78.474us 1 1 100.00
kmac_csr_aliasing 3.860s 402.217us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.810s 27.160us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.300s 31.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1484.670s 58589.595us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 385.610s 56849.016us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1770.390s 98004.990us 1 1 100.00
kmac_test_vectors_sha3_256 32.840s 9544.951us 1 1 100.00
kmac_test_vectors_sha3_384 956.460s 42952.450us 1 1 100.00
kmac_test_vectors_sha3_512 13.700s 2155.430us 1 1 100.00
kmac_test_vectors_shake_128 1379.710s 21464.976us 1 1 100.00
kmac_test_vectors_shake_256 1155.390s 34229.893us 1 1 100.00
kmac_test_vectors_kmac 1.520s 53.952us 1 1 100.00
kmac_test_vectors_kmac_xof 2.150s 133.361us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 194.360s 13845.752us 1 1 100.00
app 1 1 100.00
kmac_app 188.250s 39164.053us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 188.960s 99074.409us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 11.340s 545.542us 1 1 100.00
error 1 1 100.00
kmac_error 277.580s 39084.613us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 1.930s 328.808us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 22.000s 10288.921us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 13.580s 2861.805us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 4.090s 81.907us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 63.660s 56579.024us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.540s 49.009us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 503.870s 47512.484us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.740s 14.698us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.970s 27.260us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.900s 164.904us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.900s 164.904us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.160s 103.261us 1 1 100.00
kmac_csr_rw 0.910s 78.474us 1 1 100.00
kmac_csr_aliasing 3.860s 402.217us 1 1 100.00
kmac_same_csr_outstanding 1.340s 28.413us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.160s 103.261us 1 1 100.00
kmac_csr_rw 0.910s 78.474us 1 1 100.00
kmac_csr_aliasing 3.860s 402.217us 1 1 100.00
kmac_same_csr_outstanding 1.340s 28.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.440s 41.310us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.440s 41.310us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.440s 41.310us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.440s 41.310us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.240s 401.533us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 36.880s 3503.296us 1 1 100.00
kmac_tl_intg_err 3.630s 385.645us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.630s 385.645us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.540s 49.009us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 9.760s 3540.938us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 194.360s 13845.752us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.440s 41.310us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 36.880s 3503.296us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 36.880s 3503.296us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 36.880s 3503.296us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 9.760s 3540.938us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.540s 49.009us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 36.880s 3503.296us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 191.180s 121081.327us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 9.760s 3540.938us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 73.890s 16936.452us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) 1 test run
kmac_sideload_invalid 52430618661202947358440584686919867258432318188717568787642932780900127981300 94
UVM_INFO @ 10288920833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 53755661483745746730952021155181614917091319395862366002486339321915483011813 339
UVM_INFO @ 16936452122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---