Simulation Results: lc_ctrl/volatile_unlock_disabled

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.85 %
  • code
  • 84.46 %
  • assert
  • 95.99 %
  • func
  • 92.09 %
  • line
  • 97.80 %
  • branch
  • 96.34 %
  • cond
  • 79.43 %
  • toggle
  • 86.89 %
  • FSM
  • 61.82 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.840s 83.260us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.050s 52.372us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.950s 18.908us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.650s 42.073us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.410s 144.396us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.120s 36.785us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.950s 18.908us 1 1 100.00
lc_ctrl_csr_aliasing 1.410s 144.396us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.440s 475.733us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.940s 1193.991us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.890s 14.408us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.620s 70.905us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.670s 822.871us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.680s 1527.543us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.670s 822.871us 1 1 100.00
lc_ctrl_prog_failure 2.620s 70.905us 1 1 100.00
lc_ctrl_errors 6.680s 1527.543us 1 1 100.00
lc_ctrl_security_escalation 4.240s 231.617us 1 1 100.00
lc_ctrl_jtag_state_failure 16.700s 8160.664us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.800s 582.336us 1 1 100.00
lc_ctrl_jtag_errors 31.910s 5340.470us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.020s 1139.156us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.970s 908.492us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.800s 582.336us 1 1 100.00
lc_ctrl_jtag_errors 31.910s 5340.470us 1 1 100.00
lc_ctrl_jtag_access 4.060s 434.055us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 4.670s 3119.840us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.130s 1546.779us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.690s 84.528us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.970s 2543.354us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.700s 2933.198us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.840s 58.406us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.270s 129.775us 1 1 100.00
lc_ctrl_jtag_alert_test 1.440s 112.876us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 21.220s 1433.165us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.220s 12.381us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 68.130s 15025.214us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.120s 90.855us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.410s 106.981us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.410s 106.981us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.050s 52.372us 1 1 100.00
lc_ctrl_csr_rw 0.950s 18.908us 1 1 100.00
lc_ctrl_csr_aliasing 1.410s 144.396us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.250s 37.352us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.050s 52.372us 1 1 100.00
lc_ctrl_csr_rw 0.950s 18.908us 1 1 100.00
lc_ctrl_csr_aliasing 1.410s 144.396us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.250s 37.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.660s 930.376us 1 1 100.00
lc_ctrl_tl_intg_err 1.260s 93.902us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.260s 93.902us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.940s 1193.991us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.670s 822.871us 1 1 100.00
lc_ctrl_sec_cm 7.660s 930.376us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.670s 822.871us 1 1 100.00
lc_ctrl_sec_cm 7.660s 930.376us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.670s 822.871us 1 1 100.00
lc_ctrl_sec_cm 7.660s 930.376us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.670s 822.871us 1 1 100.00
lc_ctrl_sec_cm 7.660s 930.376us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.670s 822.871us 1 1 100.00
lc_ctrl_sec_cm 7.660s 930.376us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.670s 822.871us 1 1 100.00
lc_ctrl_sec_cm 7.660s 930.376us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.670s 822.871us 1 1 100.00
lc_ctrl_sec_cm 7.660s 930.376us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.670s 822.871us 1 1 100.00
lc_ctrl_sec_cm 7.660s 930.376us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.240s 231.617us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.440s 475.733us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.970s 908.492us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.620s 303.815us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.620s 303.815us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.530s 831.445us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.500s 463.475us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.500s 463.475us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 5.470s 287.186us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 35125319844986819332470357524038551660923977089551082690122019925330397018085 152
UVM_INFO @ 287186196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---