Simulation Results: lc_ctrl/volatile_unlock_enabled

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.56 %
  • code
  • 85.71 %
  • assert
  • 95.99 %
  • func
  • 92.99 %
  • line
  • 97.87 %
  • branch
  • 96.64 %
  • cond
  • 79.95 %
  • toggle
  • 90.44 %
  • FSM
  • 63.64 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.850s 702.791us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.820s 118.039us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.830s 17.190us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.170s 50.592us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.930s 76.666us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.130s 146.129us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.830s 17.190us 1 1 100.00
lc_ctrl_csr_aliasing 0.930s 76.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.470s 86.774us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.900s 1289.396us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.720s 37.583us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.370s 75.567us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.170s 1969.152us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.670s 945.781us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.170s 1969.152us 1 1 100.00
lc_ctrl_prog_failure 1.370s 75.567us 1 1 100.00
lc_ctrl_errors 5.670s 945.781us 1 1 100.00
lc_ctrl_security_escalation 7.920s 2498.605us 1 1 100.00
lc_ctrl_jtag_state_failure 18.810s 1600.318us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.420s 751.167us 1 1 100.00
lc_ctrl_jtag_errors 13.340s 5044.034us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.740s 59.569us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.820s 321.483us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.420s 751.167us 1 1 100.00
lc_ctrl_jtag_errors 13.340s 5044.034us 1 1 100.00
lc_ctrl_jtag_access 8.820s 1270.801us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.300s 13718.361us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.200s 577.660us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.270s 342.594us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.820s 1203.344us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.110s 514.600us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.170s 66.336us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.960s 361.355us 1 1 100.00
lc_ctrl_jtag_alert_test 1.220s 160.293us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.120s 519.472us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.990s 52.114us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 22.530s 990.143us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.830s 31.749us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.940s 511.968us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.940s 511.968us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.820s 118.039us 1 1 100.00
lc_ctrl_csr_rw 0.830s 17.190us 1 1 100.00
lc_ctrl_csr_aliasing 0.930s 76.666us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.850s 54.634us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.820s 118.039us 1 1 100.00
lc_ctrl_csr_rw 0.830s 17.190us 1 1 100.00
lc_ctrl_csr_aliasing 0.930s 76.666us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.850s 54.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.840s 234.223us 1 1 100.00
lc_ctrl_tl_intg_err 2.820s 133.631us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.820s 133.631us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.900s 1289.396us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.170s 1969.152us 1 1 100.00
lc_ctrl_sec_cm 5.840s 234.223us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.170s 1969.152us 1 1 100.00
lc_ctrl_sec_cm 5.840s 234.223us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.170s 1969.152us 1 1 100.00
lc_ctrl_sec_cm 5.840s 234.223us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.170s 1969.152us 1 1 100.00
lc_ctrl_sec_cm 5.840s 234.223us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.170s 1969.152us 1 1 100.00
lc_ctrl_sec_cm 5.840s 234.223us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.170s 1969.152us 1 1 100.00
lc_ctrl_sec_cm 5.840s 234.223us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.170s 1969.152us 1 1 100.00
lc_ctrl_sec_cm 5.840s 234.223us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.170s 1969.152us 1 1 100.00
lc_ctrl_sec_cm 5.840s 234.223us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.920s 2498.605us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.470s 86.774us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.820s 321.483us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.030s 1971.974us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.030s 1971.974us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.590s 1444.795us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.790s 227.903us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.790s 227.903us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 36.260s 31941.630us 1 1 100.00