Simulation Results: mbx

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.36 %
  • code
  • 90.11 %
  • assert
  • 96.48 %
  • func
  • 75.49 %
  • block
  • 95.93 %
  • line
  • 95.40 %
  • branch
  • 89.19 %
  • toggle
  • 85.73 %
Validation stages
V1
83.33%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 63.000s 9845.170us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 42.244us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 163.321us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 1356.721us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 29.205us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 4.809us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 163.321us 1 1 100.00
mbx_csr_aliasing 2.000s 29.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 6.000s 781.701us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 9.000s 760.350us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 20.000s 3031.842us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 17.000s 562.246us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 127.103us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 15.236us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 8.864us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 8.864us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 42.244us 1 1 100.00
mbx_csr_rw 1.000s 163.321us 1 1 100.00
mbx_csr_aliasing 2.000s 29.205us 1 1 100.00
mbx_same_csr_outstanding 2.000s 19.977us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 42.244us 1 1 100.00
mbx_csr_rw 1.000s 163.321us 1 1 100.00
mbx_csr_aliasing 2.000s 29.205us 1 1 100.00
mbx_same_csr_outstanding 2.000s 19.977us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 149.218us 1 1 100.00
mbx_sec_cm 2.000s 45.302us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 2 test runs
mbx_stress 63893451823216605703220986167251463397906860696437497366316387892010211309551 196
UVM_INFO @ 781701219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress_zero_delays 66701457877723966812961454296970970800660862381574147299172936160648070617323 672
UVM_INFO @ 760350393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 75417677741854103534883199438573501540303962684604048819226918152979466949470 85
TL item was: req: (cip_tl_seq_item@15335) { a_addr: 'hd7669490 a_data: 'h9f191806 a_mask: 'h1 a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h1 a_user: 'h25ad9 d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 8863802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 7410494209700011032124038876168262646584467982807387506448772602252110676595 86
TL item was: req: (cip_tl_seq_item@18766) { a_addr: 'h14593914 a_data: 'ha4f6c904 a_mask: 'h0 a_size: 'h0 a_param: 'h0 a_source: 'h1c a_opcode: 'h1 a_user: 'h26e10 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 4808820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---