Simulation Results: rom_ctrl/32kb

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.26 %
  • code
  • 96.04 %
  • assert
  • 96.80 %
  • func
  • 95.94 %
  • line
  • 99.46 %
  • branch
  • 97.81 %
  • cond
  • 96.73 %
  • toggle
  • 99.52 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.510s 564.736us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.490s 552.062us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.390s 130.329us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.420s 557.001us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.920s 554.920us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.110s 137.861us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.390s 130.329us 1 1 100.00
rom_ctrl_csr_aliasing 3.920s 554.920us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.930s 374.094us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.840s 554.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.920s 225.023us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 11.950s 446.975us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.920s 226.426us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.120s 237.251us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.490s 169.646us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.490s 169.646us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.490s 552.062us 1 1 100.00
rom_ctrl_csr_rw 3.390s 130.329us 1 1 100.00
rom_ctrl_csr_aliasing 3.920s 554.920us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.300s 212.387us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.490s 552.062us 1 1 100.00
rom_ctrl_csr_rw 3.390s 130.329us 1 1 100.00
rom_ctrl_csr_aliasing 3.920s 554.920us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.300s 212.387us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.110s 8083.191us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.290s 1955.772us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 97.560s 1983.299us 1 1 100.00
rom_ctrl_tl_intg_err 24.660s 308.673us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 97.560s 1983.299us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 97.560s 1983.299us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.110s 8083.191us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.110s 8083.191us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.110s 8083.191us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.110s 8083.191us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.110s 8083.191us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 97.560s 1983.299us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 97.560s 1983.299us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.510s 564.736us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.510s 564.736us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.510s 564.736us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.660s 308.673us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.110s 8083.191us 1 1 100.00
rom_ctrl_kmac_err_chk 6.920s 226.426us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.110s 8083.191us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.110s 8083.191us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 39.110s 8083.191us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.290s 1955.772us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 97.560s 1983.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 72.210s 2588.301us 1 1 100.00