Simulation Results: rom_ctrl/64kb

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.14 %
  • code
  • 97.86 %
  • assert
  • 96.66 %
  • func
  • 96.90 %
  • line
  • 99.32 %
  • branch
  • 98.91 %
  • cond
  • 97.77 %
  • toggle
  • 99.97 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.720s 1156.492us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 11.430s 544.296us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.820s 788.445us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 10.570s 1043.431us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.020s 729.097us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.590s 229.008us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.820s 788.445us 1 1 100.00
rom_ctrl_csr_aliasing 6.020s 729.097us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.880s 767.480us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.610s 300.717us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.050s 916.789us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 21.620s 3090.889us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 15.230s 554.748us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.970s 2282.898us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.970s 364.082us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.970s 364.082us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.430s 544.296us 1 1 100.00
rom_ctrl_csr_rw 5.820s 788.445us 1 1 100.00
rom_ctrl_csr_aliasing 6.020s 729.097us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.590s 228.766us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.430s 544.296us 1 1 100.00
rom_ctrl_csr_rw 5.820s 788.445us 1 1 100.00
rom_ctrl_csr_aliasing 6.020s 729.097us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.590s 228.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.070s 2559.490us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.200s 1585.388us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 433.550s 1271.829us 1 1 100.00
rom_ctrl_tl_intg_err 50.450s 389.736us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 433.550s 1271.829us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 433.550s 1271.829us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.070s 2559.490us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.070s 2559.490us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.070s 2559.490us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.070s 2559.490us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.070s 2559.490us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 433.550s 1271.829us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 433.550s 1271.829us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.720s 1156.492us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.720s 1156.492us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.720s 1156.492us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 50.450s 389.736us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.070s 2559.490us 1 1 100.00
rom_ctrl_kmac_err_chk 15.230s 554.748us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.070s 2559.490us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.070s 2559.490us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 111.070s 2559.490us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.200s 1585.388us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 433.550s 1271.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 45.150s 1784.764us 1 1 100.00