Simulation Results: rstmgr

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.94 %
  • code
  • 99.22 %
  • assert
  • 97.62 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.64 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.240s 59.029us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.210s 63.950us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.950s 38.191us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.910s 104.708us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.500s 49.702us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.620s 97.192us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.950s 38.191us 1 1 100.00
rstmgr_csr_aliasing 1.500s 49.702us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.410s 203.962us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.910s 37.546us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.870s 54.019us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.210s 591.936us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.210s 591.936us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.210s 591.936us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.210s 591.936us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 24.690s 3725.278us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.090s 37.576us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.400s 58.426us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.400s 58.426us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.210s 63.950us 1 1 100.00
rstmgr_csr_rw 0.950s 38.191us 1 1 100.00
rstmgr_csr_aliasing 1.500s 49.702us 1 1 100.00
rstmgr_same_csr_outstanding 0.970s 43.159us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.210s 63.950us 1 1 100.00
rstmgr_csr_rw 0.950s 38.191us 1 1 100.00
rstmgr_csr_aliasing 1.500s 49.702us 1 1 100.00
rstmgr_same_csr_outstanding 0.970s 43.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 14.950s 3430.823us 1 1 100.00
rstmgr_tl_intg_err 3.990s 623.232us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 14.950s 3430.823us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 14.950s 3430.823us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.990s 623.232us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.170s 59.886us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.400s 420.395us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.220s 291.618us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 14.950s 3430.823us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.950s 38.191us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.950s 38.191us 1 1 100.00