Simulation Results: rv_dm/use_dmi_interface

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.27 %
  • code
  • 73.72 %
  • assert
  • 96.16 %
  • func
  • 46.93 %
  • line
  • 90.16 %
  • branch
  • 74.79 %
  • cond
  • 76.32 %
  • toggle
  • 71.09 %
  • FSM
  • 56.25 %
Validation stages
V1
96.30%
V2
69.57%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 7.650s 6154.695us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 1.440s 519.706us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 1.360s 640.246us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 5.520s 3142.674us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 1.100s 640.050us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 2.000s 3066.474us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 7.020s 5449.024us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 2.620s 3998.800us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 21.970s 47656.068us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 1.410s 1302.545us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 0.910s 137.593us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 0.890s 518.528us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 1.030s 222.439us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 0.720s 117.336us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 0.740s 278.870us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 0.840s 268.533us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 1.030s 254.055us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 1.410s 1302.545us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 0.740s 172.869us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.190s 264.962us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 0.890s 518.528us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 1.000s 121.409us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 1.200s 74.504us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.730s 160.760us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 50.190s 14972.408us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 55.790s 26927.045us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 2.420s 110.290us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 55.790s 26927.045us 1 1 100.00
rv_dm_csr_rw 1.730s 160.760us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.660s 55.471us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.880s 227.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 7.650s 6154.695us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 1.080s 228.552us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.850s 170.643us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 0.770s 248.381us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 1.010s 368.244us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 9.730s 9830.026us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 0.970s 141.990us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 1.930s 3538.382us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 9.380s 9870.856us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 0.900s 385.874us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 3.120s 2075.628us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 1.050s 665.488us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 0.660s 280.006us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 5.750s 8784.120us 1 1 100.00
rv_dm_tap_fsm_rand_reset 75.080s 7801.089us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.860s 85.645us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 0.720s 58.981us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.880s 115.636us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 2.850s 167.033us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 2.850s 167.033us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 55.790s 26927.045us 1 1 100.00
rv_dm_csr_hw_reset 1.200s 74.504us 1 1 100.00
rv_dm_csr_rw 1.730s 160.760us 1 1 100.00
rv_dm_same_csr_outstanding 7.170s 5893.176us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 55.790s 26927.045us 1 1 100.00
rv_dm_csr_hw_reset 1.200s 74.504us 1 1 100.00
rv_dm_csr_rw 1.730s 160.760us 1 1 100.00
rv_dm_same_csr_outstanding 7.170s 5893.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 1.800s 662.963us 1 1 100.00
rv_dm_tl_intg_err 15.930s 3091.119us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 15.930s 3091.119us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 3.120s 2075.628us 1 1 100.00
rv_dm_debug_disabled 0.840s 31.332us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 3.120s 2075.628us 1 1 100.00
rv_dm_debug_disabled 0.840s 31.332us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 7.650s 6154.695us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 1.210s 432.302us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.760s 51.710us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.760s 51.710us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 1.210s 432.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 23.470s 1386.032us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 407.770s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared: 2 test runs
rv_dm_sba_tl_access 90262400331303074491311220693318253238618238939179638819815143331007778655437 86
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @5278
rv_dm_autoincr_sba_tl_access 2779165269636797540906218312819511476734092660289512405472331570183099992464 131
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @16396
Error-[CNST-CIF] Constraints inconsistency failure 2 test runs
rv_dm_delayed_resp_sba_tl_access 60489590385113397863503114250308149137940086724761386311767045584107320442850 133
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
rv_dm_bad_sba_tl_access 84015351820375621844327963457354717066263398170423269568802077474845153007403 163
src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*]) 2 test runs
rv_dm_mem_tl_access_resuming 21915429784166090937966194515946090519781256404478614128128342108339914176112 77
UVM_INFO @ 222439318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 64896618266363774056416943953265487819294070836624171213617380053929125265314 118
UVM_INFO @ 1386032359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*]) 2 test runs
rv_dm_hart_unavail 25525445831480770914294145175056700896455691762130866378734022769173026116746 77
UVM_INFO @ 280006344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 111431433672766005733869125410488224745500662797024608984326825503081311594971 78
UVM_INFO @ 58981478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 1 test run
rv_dm_jtag_dmi_debug_disabled 6677758928478436562140807420013614703020587581134361685244546081166027214426 77
UVM_INFO @ 385874391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 34491810098568231633949468248054252943788339180424451159667488044126735121796 77
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---