Simulation Results: rv_timer

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.55 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 83.82 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.580s 35.614us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.700s 20.244us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.550s 14.275us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.120s 37.369us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.680s 95.299us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.610s 49.963us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.550s 14.275us 1 1 100.00
rv_timer_csr_aliasing 0.680s 95.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.720s 2143.994us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.890s 1113.141us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 11.410s 15793.767us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 11.410s 15793.767us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.630s 39.235us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.550s 15.618us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.620s 26.531us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 0.990s 83.666us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 0.990s 83.666us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.700s 20.244us 1 1 100.00
rv_timer_csr_rw 0.550s 14.275us 1 1 100.00
rv_timer_csr_aliasing 0.680s 95.299us 1 1 100.00
rv_timer_same_csr_outstanding 0.650s 60.178us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.700s 20.244us 1 1 100.00
rv_timer_csr_rw 0.550s 14.275us 1 1 100.00
rv_timer_csr_aliasing 0.680s 95.299us 1 1 100.00
rv_timer_same_csr_outstanding 0.650s 60.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.900s 93.757us 1 1 100.00
rv_timer_tl_intg_err 1.110s 631.131us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.110s 631.131us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.530s 46.953us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.620s 282.551us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 17.260s 6285.738us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 52938502101707325057077914981407863464420390407999747179067283624902877563276 76
UVM_INFO @ 282550642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 83308771679593381845072611649914982807384188419365667479534876242551864392088 75
UVM_INFO @ 2143994167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---