Simulation Results: spi_device/1r1w

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.01 %
  • code
  • 93.07 %
  • assert
  • 94.76 %
  • func
  • 70.19 %
  • line
  • 99.04 %
  • branch
  • 98.21 %
  • cond
  • 95.56 %
  • toggle
  • 83.19 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 20.390s 5005.422us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.800s 18.774us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.770s 139.141us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 26.800s 3030.230us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 14.570s 1205.394us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.630s 228.280us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.770s 139.141us 1 1 100.00
spi_device_csr_aliasing 14.570s 1205.394us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.650s 30.333us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.480s 46.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.730s 18.082us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.670s 1.337us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.750s 5.546us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.830s 72.966us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.830s 72.966us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 5.040s 10974.850us 1 1 100.00
spi_device_tpm_sts_read 0.920s 108.064us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 27.300s 33300.306us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 7.440s 3019.328us 1 1 100.00
spi_device_flash_all 37.930s 20583.513us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 11.170s 21030.398us 1 1 100.00
spi_device_flash_all 37.930s 20583.513us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 11.170s 21030.398us 1 1 100.00
spi_device_flash_all 37.930s 20583.513us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 37.930s 20583.513us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.610s 193.471us 1 1 100.00
spi_device_flash_all 37.930s 20583.513us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.610s 193.471us 1 1 100.00
spi_device_flash_all 37.930s 20583.513us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.610s 193.471us 1 1 100.00
spi_device_flash_all 37.930s 20583.513us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.610s 193.471us 1 1 100.00
spi_device_flash_all 37.930s 20583.513us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.610s 193.471us 1 1 100.00
spi_device_flash_all 37.930s 20583.513us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 14.280s 10438.144us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 4.830s 385.059us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 4.830s 385.059us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 4.830s 385.059us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 10.470s 872.120us 1 1 100.00
spi_device_read_buffer_direct 4.140s 1240.791us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 4.830s 385.059us 1 1 100.00
spi_device_flash_all 37.930s 20583.513us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 37.930s 20583.513us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 37.930s 20583.513us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.260s 607.165us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.260s 607.165us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 20.390s 5005.422us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 269.260s 50639.540us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 19.460s 4506.139us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.680s 32.322us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.790s 13.882us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.070s 665.086us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.070s 665.086us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.800s 18.774us 1 1 100.00
spi_device_csr_rw 1.770s 139.141us 1 1 100.00
spi_device_csr_aliasing 14.570s 1205.394us 1 1 100.00
spi_device_same_csr_outstanding 2.890s 62.656us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.800s 18.774us 1 1 100.00
spi_device_csr_rw 1.770s 139.141us 1 1 100.00
spi_device_csr_aliasing 14.570s 1205.394us 1 1 100.00
spi_device_same_csr_outstanding 2.890s 62.656us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.890s 213.198us 1 1 100.00
spi_device_tl_intg_err 15.470s 3386.241us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 15.470s 3386.241us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 2.880s 192.190us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 55306259929139913123740286288484849721379564226443131974205160668309324786462 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1129700 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1129700 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[937])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 9640105640800617478237107909686420204095667165066732134409745122087988882881 76
UVM_ERROR @ 3312922 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf481b1 [111101001000000110110001] vs 0x0 [0])
UVM_ERROR @ 3391922 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2c77d6 [1011000111011111010110] vs 0x0 [0])
UVM_ERROR @ 3451922 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd5db52 [110101011101101101010010] vs 0x0 [0])
UVM_ERROR @ 3549922 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x648607 [11001001000011000000111] vs 0x0 [0])