Simulation Results: spi_host

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.42 %
  • code
  • 94.88 %
  • assert
  • 94.13 %
  • func
  • 88.24 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 5.000s 406.773us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 269.726us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 41.804us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 1022.542us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 72.751us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 3.000s 26.206us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 41.804us 1 1 100.00
spi_host_csr_aliasing 1.000s 72.751us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 20.731us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 51.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 23.451us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 1.000s 46.899us 1 1 100.00
spi_host_error_cmd 1.000s 98.002us 1 1 100.00
spi_host_event 42.000s 5882.799us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 101.987us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 101.987us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 101.987us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 34.340us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 57.122us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 101.987us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 101.987us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 5.000s 406.773us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 5.000s 406.773us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 8.000s 539.351us 1 1 100.00
spien 1 1 100.00
spi_host_spien 10.000s 2346.883us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 20.000s 2039.352us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 87.088us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 1.000s 46.899us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 29.461us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 47.145us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 462.217us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 462.217us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 269.726us 1 1 100.00
spi_host_csr_rw 2.000s 41.804us 1 1 100.00
spi_host_csr_aliasing 1.000s 72.751us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 39.500us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 269.726us 1 1 100.00
spi_host_csr_rw 2.000s 41.804us 1 1 100.00
spi_host_csr_aliasing 1.000s 72.751us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 39.500us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 261.823us 1 1 100.00
spi_host_sec_cm 2.000s 133.612us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 261.823us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 80.000s 4420.092us 1 1 100.00