Simulation Results: sram_ctrl/main

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.85 %
  • code
  • 95.97 %
  • assert
  • 96.19 %
  • func
  • 92.40 %
  • block
  • 95.07 %
  • line
  • 95.55 %
  • branch
  • 92.22 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 1400.956us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 34.291us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.871us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 600.415us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 27.068us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 362.703us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 15.871us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 27.068us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 106.000s 41400.447us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 70.000s 2087.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 36.000s 8324.161us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 108.000s 3793.941us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 132.000s 9916.135us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 68.000s 53749.917us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 20.000s 10922.152us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 11.000s 2334.966us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 2460.819us 1 1 100.00
sram_ctrl_partial_access_b2b 141.000s 37916.014us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 7.000s 11104.532us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 693.222us 1 1 100.00
sram_ctrl_throughput_w_readback 7.000s 11177.586us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 4726.634us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1308.873us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 323.000s 129273.019us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 26.228us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 417.103us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 417.103us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 34.291us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.871us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 27.068us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 29.447us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 34.291us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.871us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 27.068us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 29.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 3736.800us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 745.184us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 483.931us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 745.184us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 483.931us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 4726.634us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 4726.634us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.871us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 11.000s 2334.966us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 2334.966us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 2334.966us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 20.000s 10922.152us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 1334.162us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 3736.800us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 697.188us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 1400.956us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 1400.956us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 11.000s 2334.966us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 745.184us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 20.000s 10922.152us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 745.184us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 745.184us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 1400.956us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 745.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
sram_ctrl_stress_all_with_rand_reset 28.000s 5420.577us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (tl_host_driver.sv:121) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_stress_all_with_rand_reset 4012367714527745911247899959523518353826627997205970141330769535390321424856 159
UVM_INFO @ 5420576940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---