Simulation Results: uart

 
05/05/2026 19:39:24 DVSim: v1.34.0 sha: abb01fa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.99 %
  • code
  • 95.18 %
  • assert
  • 97.12 %
  • func
  • 56.66 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 93.82 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.590s 293.656us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.870s 1068.153us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.660s 16.789us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.240s 131.406us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.730s 28.030us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.740s 99.252us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.660s 16.789us 1 1 100.00
uart_csr_aliasing 0.730s 28.030us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 25.060s 27516.922us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.590s 293.656us 1 1 100.00
uart_tx_rx 25.060s 27516.922us 1 1 100.00
parity_error 2 2 100.00
uart_intr 10.640s 18026.899us 1 1 100.00
uart_rx_parity_err 178.010s 129237.963us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 25.060s 27516.922us 1 1 100.00
uart_intr 10.640s 18026.899us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 86.310s 75238.743us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 67.860s 119048.548us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 25.760s 247103.388us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 10.640s 18026.899us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 10.640s 18026.899us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 10.640s 18026.899us 1 1 100.00
perf 1 1 100.00
uart_perf 252.250s 11372.749us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 12.360s 7293.848us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 12.360s 7293.848us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 5.640s 6845.744us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.290s 39621.836us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.270s 959.777us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 24.310s 4862.615us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 128.450s 178801.392us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 367.460s 317775.033us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.590s 46.585us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.650s 37.595us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.380s 102.208us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.380s 102.208us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.870s 1068.153us 1 1 100.00
uart_csr_rw 0.660s 16.789us 1 1 100.00
uart_csr_aliasing 0.730s 28.030us 1 1 100.00
uart_same_csr_outstanding 0.720s 32.525us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.870s 1068.153us 1 1 100.00
uart_csr_rw 0.660s 16.789us 1 1 100.00
uart_csr_aliasing 0.730s 28.030us 1 1 100.00
uart_same_csr_outstanding 0.720s 32.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.060s 66.526us 1 1 100.00
uart_tl_intg_err 1.100s 53.176us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.100s 53.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 24.360s 12843.383us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 45599988774568243265593430871946330458975385231469840703714921800010266998836 76
UVM_ERROR @ 2886837096 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2886857504 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (160 [0xa0] vs 247 [0xf7]) reg name: uart_reg_block.rdata
UVM_ERROR @ 2977040456 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2977040456 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_stress_all_with_rand_reset 13406431413588995072199864372970890913694433385807377351945945285928999330051 163
UVM_ERROR @ 11861208638 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 11862416981 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 11865542006 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 11865542006 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0