Simulation Results: ac_range_check

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.87 %
  • code
  • 93.06 %
  • assert
  • 97.75 %
  • func
  • 57.79 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 31.000s 5603.266us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 43.000s 2197.604us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 48.436us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 98.457us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 32.000s 9808.682us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 19.000s 3935.311us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 22.015us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 98.457us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 3935.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 24.100us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 23.000s 5154.687us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 89.000s 1784.377us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 16.435us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 14.369us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 213.845us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 213.845us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 48.436us 1 1 100.00
ac_range_check_csr_rw 2.000s 98.457us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 3935.311us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 249.002us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 48.436us 1 1 100.00
ac_range_check_csr_rw 2.000s 98.457us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 3935.311us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 249.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 1774.253us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 1774.253us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 1774.253us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 1774.253us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 81.000s 39453.076us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 37.715us 1 1 100.00
ac_range_check_tl_intg_err 8.000s 604.872us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 230.000s 2728.573us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 23.000s 412.047us 1 1 100.00