Simulation Results: aes/gcm_masked

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.95 %
  • code
  • 95.75 %
  • assert
  • 98.29 %
  • func
  • 66.82 %
  • block
  • 95.94 %
  • line
  • 97.61 %
  • branch
  • 89.92 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 100.700us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 73.500us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 109.772us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 77.426us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 1566.209us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 235.257us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 157.103us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 77.426us 1 1 100.00
aes_csr_aliasing 2.000s 235.257us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 73.500us 1 1 100.00
aes_config_error 9.000s 617.911us 1 1 100.00
aes_stress 4.000s 104.212us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 73.500us 1 1 100.00
aes_config_error 9.000s 617.911us 1 1 100.00
aes_stress 4.000s 104.212us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 104.212us 1 1 100.00
aes_b2b 16.000s 333.639us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 104.212us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 73.500us 1 1 100.00
aes_config_error 9.000s 617.911us 1 1 100.00
aes_stress 4.000s 104.212us 1 1 100.00
aes_alert_reset 18.000s 10262.075us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 89.163us 1 1 100.00
aes_config_error 9.000s 617.911us 1 1 100.00
aes_alert_reset 18.000s 10262.075us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 98.481us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 9.000s 1489.493us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 9.000s 710.159us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 18.000s 10262.075us 0 1 0.00
stress 1 1 100.00
aes_stress 4.000s 104.212us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 104.212us 1 1 100.00
aes_sideload 2.000s 149.757us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 166.106us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 20.000s 3388.508us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 152.959us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 57.162us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 69.904us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 69.904us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 109.772us 1 1 100.00
aes_csr_rw 2.000s 77.426us 1 1 100.00
aes_csr_aliasing 2.000s 235.257us 1 1 100.00
aes_same_csr_outstanding 2.000s 84.142us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 109.772us 1 1 100.00
aes_csr_rw 2.000s 77.426us 1 1 100.00
aes_csr_aliasing 2.000s 235.257us 1 1 100.00
aes_same_csr_outstanding 2.000s 84.142us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 6.000s 116.942us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 19.000s 10054.848us 0 1 0.00
aes_control_fi 1.000s 84.114us 1 1 100.00
aes_cipher_fi 2.000s 53.259us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 113.408us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 113.408us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 113.408us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 113.408us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 295.316us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 2045.483us 1 1 100.00
aes_tl_intg_err 3.000s 286.188us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 286.188us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 18.000s 10262.075us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 113.408us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 113.408us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 73.500us 1 1 100.00
aes_stress 4.000s 104.212us 1 1 100.00
aes_alert_reset 18.000s 10262.075us 0 1 0.00
aes_core_fi 4.000s 107.217us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 152.959us 1 1 100.00
aes_config_error 9.000s 617.911us 1 1 100.00
aes_stress 4.000s 104.212us 1 1 100.00
aes_core_fi 4.000s 107.217us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 113.408us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 95.548us 1 1 100.00
aes_stress 4.000s 104.212us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 104.212us 1 1 100.00
aes_sideload 2.000s 149.757us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 95.548us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 95.548us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 95.548us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 95.548us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 95.548us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 104.212us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 104.212us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 19.000s 10054.848us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 19.000s 10054.848us 0 1 0.00
aes_control_fi 1.000s 84.114us 1 1 100.00
aes_cipher_fi 2.000s 53.259us 1 1 100.00
aes_ctr_fi 2.000s 59.301us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 19.000s 10054.848us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 19.000s 10054.848us 0 1 0.00
aes_control_fi 1.000s 84.114us 1 1 100.00
aes_cipher_fi 2.000s 53.259us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 53.259us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 19.000s 10054.848us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 19.000s 10054.848us 0 1 0.00
aes_control_fi 1.000s 84.114us 1 1 100.00
aes_ctr_fi 2.000s 59.301us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 19.000s 10054.848us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 19.000s 10054.848us 0 1 0.00
aes_control_fi 1.000s 84.114us 1 1 100.00
aes_cipher_fi 2.000s 53.259us 1 1 100.00
aes_ctr_fi 2.000s 59.301us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 18.000s 10262.075us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 19.000s 10054.848us 0 1 0.00
aes_control_fi 1.000s 84.114us 1 1 100.00
aes_cipher_fi 2.000s 53.259us 1 1 100.00
aes_ctr_fi 2.000s 59.301us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 19.000s 10054.848us 0 1 0.00
aes_control_fi 1.000s 84.114us 1 1 100.00
aes_cipher_fi 2.000s 53.259us 1 1 100.00
aes_ctr_fi 2.000s 59.301us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 19.000s 10054.848us 0 1 0.00
aes_control_fi 1.000s 84.114us 1 1 100.00
aes_ctr_fi 2.000s 59.301us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 2.000s 72.646us 1 1 100.00
aes_fi 19.000s 10054.848us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 19.000s 10054.848us 0 1 0.00
aes_control_fi 1.000s 84.114us 1 1 100.00
aes_cipher_fi 2.000s 53.259us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 55.000s 1254.890us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred! 1 test run
aes_alert_reset 52467993671703523961497551749759638551750191597256242870573427092076979715731 5479
UVM_INFO @ 10262075297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred! 1 test run
aes_fi 57726828674124487905020279282448437083110214476583345306094668205949070127522 4963
UVM_INFO @ 10054847608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:307) virtual_sequencer [aes_stress_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG 1 test run
aes_stress_all_with_rand_reset 98348870629361169257738416643206047507398794634139662746762475730183689148072 1799
UVM_INFO @ 1254890031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---