Simulation Results: aes/gcm_unmasked

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.16 %
  • code
  • 90.91 %
  • assert
  • 97.75 %
  • func
  • 66.82 %
  • block
  • 90.41 %
  • line
  • 92.41 %
  • branch
  • 82.45 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
88.24%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 121.350us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 99.430us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 81.632us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 75.143us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 767.463us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 144.444us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 67.508us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 75.143us 1 1 100.00
aes_csr_aliasing 3.000s 144.444us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 99.430us 1 1 100.00
aes_config_error 2.000s 134.862us 1 1 100.00
aes_stress 2.000s 83.888us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 99.430us 1 1 100.00
aes_config_error 2.000s 134.862us 1 1 100.00
aes_stress 2.000s 83.888us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 83.888us 1 1 100.00
aes_b2b 8.000s 167.071us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 83.888us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 99.430us 1 1 100.00
aes_config_error 2.000s 134.862us 1 1 100.00
aes_stress 2.000s 83.888us 1 1 100.00
aes_alert_reset 33.000s 10009.927us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 81.824us 1 1 100.00
aes_config_error 2.000s 134.862us 1 1 100.00
aes_alert_reset 33.000s 10009.927us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 64.342us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 121.898us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 33.000s 10009.927us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 83.888us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 83.888us 1 1 100.00
aes_sideload 2.000s 118.233us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 108.152us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 19.000s 10021.980us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 123.444us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 106.206us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 106.206us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 81.632us 1 1 100.00
aes_csr_rw 1.000s 75.143us 1 1 100.00
aes_csr_aliasing 3.000s 144.444us 1 1 100.00
aes_same_csr_outstanding 2.000s 103.492us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 81.632us 1 1 100.00
aes_csr_rw 1.000s 75.143us 1 1 100.00
aes_csr_aliasing 3.000s 144.444us 1 1 100.00
aes_same_csr_outstanding 2.000s 103.492us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 406.257us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 28.000s 10003.966us 0 1 0.00
aes_control_fi 2.000s 70.143us 1 1 100.00
aes_cipher_fi 2.000s 91.746us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 135.640us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 135.640us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 135.640us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 135.640us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 245.980us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 556.685us 1 1 100.00
aes_tl_intg_err 2.000s 183.547us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 183.547us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 33.000s 10009.927us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 135.640us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 135.640us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 99.430us 1 1 100.00
aes_stress 2.000s 83.888us 1 1 100.00
aes_alert_reset 33.000s 10009.927us 0 1 0.00
aes_core_fi 2.000s 89.463us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 134.862us 1 1 100.00
aes_stress 2.000s 83.888us 1 1 100.00
aes_core_fi 2.000s 89.463us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 135.640us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 92.388us 1 1 100.00
aes_stress 2.000s 83.888us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 83.888us 1 1 100.00
aes_sideload 2.000s 118.233us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 92.388us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 92.388us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 92.388us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 92.388us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 92.388us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 83.888us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 83.888us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 28.000s 10003.966us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 28.000s 10003.966us 0 1 0.00
aes_control_fi 2.000s 70.143us 1 1 100.00
aes_cipher_fi 2.000s 91.746us 1 1 100.00
aes_ctr_fi 2.000s 56.088us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 28.000s 10003.966us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 28.000s 10003.966us 0 1 0.00
aes_control_fi 2.000s 70.143us 1 1 100.00
aes_cipher_fi 2.000s 91.746us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 91.746us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 28.000s 10003.966us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 28.000s 10003.966us 0 1 0.00
aes_control_fi 2.000s 70.143us 1 1 100.00
aes_ctr_fi 2.000s 56.088us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 28.000s 10003.966us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 28.000s 10003.966us 0 1 0.00
aes_control_fi 2.000s 70.143us 1 1 100.00
aes_cipher_fi 2.000s 91.746us 1 1 100.00
aes_ctr_fi 2.000s 56.088us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 33.000s 10009.927us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 28.000s 10003.966us 0 1 0.00
aes_control_fi 2.000s 70.143us 1 1 100.00
aes_cipher_fi 2.000s 91.746us 1 1 100.00
aes_ctr_fi 2.000s 56.088us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 28.000s 10003.966us 0 1 0.00
aes_control_fi 2.000s 70.143us 1 1 100.00
aes_cipher_fi 2.000s 91.746us 1 1 100.00
aes_ctr_fi 2.000s 56.088us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 28.000s 10003.966us 0 1 0.00
aes_control_fi 2.000s 70.143us 1 1 100.00
aes_ctr_fi 2.000s 56.088us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 28.000s 10003.966us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 28.000s 10003.966us 0 1 0.00
aes_control_fi 2.000s 70.143us 1 1 100.00
aes_cipher_fi 2.000s 91.746us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 21.000s 3203.802us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred! 2 test runs
aes_alert_reset 40325799946977032763666596696649958043801476920965101614673039872226314552261 2887
UVM_INFO @ 10009927121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 25106012551296414019356338923241260606821802458470140031943937968474155066156 740
UVM_INFO @ 10021979622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred! 1 test run
aes_fi 36952727516423115926714021541295618497757153007560769642185111360614825824885 470
UVM_INFO @ 10003966393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 31693568179991278413761223687446479880094489660233155260750046461554455144884 1699
UVM_INFO @ 3203802112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---