Simulation Results: alert_handler

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.38 %
  • code
  • 91.85 %
  • assert
  • 98.11 %
  • func
  • 78.17 %
  • line
  • 99.69 %
  • branch
  • 98.58 %
  • cond
  • 91.65 %
  • toggle
  • 95.12 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 17.040s 5737.901us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.630s 289.939us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 7.000s 487.901us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 318.710s 25829.818us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 97.340s 9376.280us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.770s 330.925us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 7.000s 487.901us 1 1 100.00
alert_handler_csr_aliasing 97.340s 9376.280us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 44.130s 929.818us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 9.460s 187.230us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1152.060s 100845.418us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 3.800s 149.423us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 17.040s 5737.901us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 50.750s 1266.336us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 17.030s 305.908us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 245.620s 8347.837us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1564.010s 61496.090us 1 1 100.00
alert_handler_lpg_stub_clk 1020.210s 23317.162us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 267.910s 23571.259us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 37.470s 1247.488us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.820s 93.924us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.270s 7.623us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.780s 307.043us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.780s 307.043us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.630s 289.939us 1 1 100.00
alert_handler_csr_rw 7.000s 487.901us 1 1 100.00
alert_handler_csr_aliasing 97.340s 9376.280us 1 1 100.00
alert_handler_same_csr_outstanding 16.170s 535.446us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.630s 289.939us 1 1 100.00
alert_handler_csr_rw 7.000s 487.901us 1 1 100.00
alert_handler_csr_aliasing 97.340s 9376.280us 1 1 100.00
alert_handler_same_csr_outstanding 16.170s 535.446us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 280.100s 11476.444us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 280.100s 11476.444us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 280.100s 11476.444us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 280.100s 11476.444us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 484.170s 5211.064us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 17.540s 461.916us 1 1 100.00
alert_handler_tl_intg_err 28.190s 1076.584us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 28.190s 1076.584us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 280.100s 11476.444us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 17.040s 5737.901us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 17.040s 5737.901us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 17.040s 5737.901us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 17.040s 5737.901us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 3.800s 149.423us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1564.010s 61496.090us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 3.800s 149.423us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1152.060s 100845.418us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1152.060s 100845.418us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.540s 461.916us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.540s 461.916us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.540s 461.916us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.540s 461.916us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 17.540s 461.916us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.540s 461.916us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.540s 461.916us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.540s 461.916us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 17.540s 461.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 62.650s 15552.075us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 87532943657313440976188790200173990323836638182333719780209589944277834792725 112
UVM_INFO @ 15552074915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---