| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| aon_timer_smoke | 0.910s | 716.194us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_hw_reset | 1.490s | 693.696us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aon_timer_csr_rw | 0.890s | 451.360us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aon_timer_csr_bit_bash | 15.980s | 14000.913us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aon_timer_csr_aliasing | 1.360s | 522.026us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 0.920s | 353.608us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aon_timer_csr_rw | 0.890s | 451.360us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 1.360s | 522.026us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| aon_timer_mem_walk | 1.000s | 417.822us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| aon_timer_mem_partial_access | 0.960s | 435.662us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 1 | 1 | 100.00 | |||
| aon_timer_prescaler | 5.700s | 20776.706us | 1 | 1 | 100.00 | |
| jump | 1 | 1 | 100.00 | |||
| aon_timer_jump | 1.510s | 591.311us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| aon_timer_stress_all | 114.320s | 103494.872us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aon_timer_alert_test | 0.970s | 394.455us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| aon_timer_intr_test | 0.760s | 394.807us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aon_timer_tl_errors | 1.500s | 588.994us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aon_timer_tl_errors | 1.500s | 588.994us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aon_timer_csr_hw_reset | 1.490s | 693.696us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 0.890s | 451.360us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 1.360s | 522.026us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 2.450s | 2345.252us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aon_timer_csr_hw_reset | 1.490s | 693.696us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 0.890s | 451.360us | 1 | 1 | 100.00 | |
| aon_timer_csr_aliasing | 1.360s | 522.026us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 2.450s | 2345.252us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| aon_timer_sec_cm | 1.770s | 4130.714us | 1 | 1 | 100.00 | |
| aon_timer_tl_intg_err | 3.990s | 8264.316us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| aon_timer_tl_intg_err | 3.990s | 8264.316us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 1 | 1 | 100.00 | |||
| aon_timer_smoke_max_thold | 0.900s | 562.508us | 1 | 1 | 100.00 | |
| min_threshold | 1 | 1 | 100.00 | |||
| aon_timer_smoke_min_thold | 1.040s | 659.469us | 1 | 1 | 100.00 | |
| wkup_count_hi_cdc | 1 | 1 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 8.500s | 4088.003us | 1 | 1 | 100.00 | |
| custom_intr | 1 | 1 | 100.00 | |||
| aon_timer_custom_intr | 1.360s | 637.153us | 1 | 1 | 100.00 | |
| alternating_on_off | 1 | 1 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 7.420s | 4254.295us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 8.620s | 12291.197us | 1 | 1 | 100.00 | |