Simulation Results: csrng

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.95 %
  • code
  • 92.36 %
  • assert
  • 93.23 %
  • func
  • 75.26 %
  • block
  • 97.08 %
  • line
  • 97.76 %
  • branch
  • 92.67 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 56.279us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 40.786us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 15.645us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 9.000s 221.995us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 112.384us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 25.983us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 15.645us 1 1 100.00
csrng_csr_aliasing 3.000s 112.384us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
alerts 1 1 100.00
csrng_alert 11.000s 652.354us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 10.000s 788.169us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 10.000s 788.169us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 155.000s 9717.776us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 20.809us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 50.627us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 78.807us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 78.807us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 40.786us 1 1 100.00
csrng_csr_rw 2.000s 15.645us 1 1 100.00
csrng_csr_aliasing 3.000s 112.384us 1 1 100.00
csrng_same_csr_outstanding 4.000s 47.334us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 40.786us 1 1 100.00
csrng_csr_rw 2.000s 15.645us 1 1 100.00
csrng_csr_aliasing 3.000s 112.384us 1 1 100.00
csrng_same_csr_outstanding 4.000s 47.334us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 7.000s 325.678us 1 1 100.00
csrng_tl_intg_err 8.000s 162.300us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 3.000s 20.713us 1 1 100.00
csrng_csr_rw 2.000s 15.645us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 11.000s 652.354us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 155.000s 9717.776us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
csrng_sec_cm 7.000s 325.678us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
csrng_sec_cm 7.000s 325.678us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
csrng_sec_cm 7.000s 325.678us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
csrng_sec_cm 7.000s 325.678us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
csrng_sec_cm 7.000s 325.678us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 11.000s 652.354us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 155.000s 9717.776us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 11.000s 652.354us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 8.000s 162.300us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
csrng_sec_cm 7.000s 325.678us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
csrng_sec_cm 7.000s 325.678us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 293.941us 1 1 100.00
csrng_err 1.000s 26.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 10802.056s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 23342522429725519681002634957273078998471235614947054090113137131738287305136 150
UVM_INFO @ 788168849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 36234418912770909009080545327400368884186306222429702962064136443147111625073 None