Simulation Results: dma

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.96 %
  • code
  • 92.17 %
  • assert
  • 95.97 %
  • func
  • 60.73 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 8.000s 1280.909us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 6.000s 818.612us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 1364.597us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 76.583us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 22.019us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 6.000s 1022.620us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 6.000s 840.786us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 96.977us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 22.019us 1 1 100.00
dma_csr_aliasing 6.000s 840.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 38.000s 30801.385us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 193.000s 39175.740us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 75.000s 6096.111us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 75.000s 6096.111us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 193.000s 39175.740us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 775.000s 342812.666us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 75.000s 6096.111us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 16.000s 5078.149us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 239.000s 19305.973us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 25.382us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 15.476us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 881.998us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 881.998us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 76.583us 1 1 100.00
dma_csr_rw 2.000s 22.019us 1 1 100.00
dma_csr_aliasing 6.000s 840.786us 1 1 100.00
dma_same_csr_outstanding 2.000s 63.363us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 76.583us 1 1 100.00
dma_csr_rw 2.000s 22.019us 1 1 100.00
dma_csr_aliasing 6.000s 840.786us 1 1 100.00
dma_same_csr_outstanding 2.000s 63.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 20.000s 1094.080us 1 1 100.00
dma_generic_stress 775.000s 342812.666us 1 1 100.00
dma_handshake_stress 75.000s 6096.111us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 1370.217us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 439.933us 1 1 100.00
dma_sec_cm 1.000s 11.112us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 53.000s 5748.474us 1 1 100.00
dma_longer_transfer 8.000s 1283.496us 1 1 100.00
dma_stress_all_with_rand_reset 12.000s 3866.170us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 69104243414849492796818100569034334405896612489326288972945812413997176614320 114
UVM_INFO @ 3866170272ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---