Simulation Results: edn/edn0

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.26 %
  • code
  • 83.88 %
  • assert
  • 96.96 %
  • func
  • 80.95 %
  • line
  • 97.99 %
  • branch
  • 93.72 %
  • cond
  • 88.68 %
  • toggle
  • 85.79 %
  • FSM
  • 53.23 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.920s 19.793us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.880s 17.272us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.780s 33.539us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.880s 886.902us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.380s 33.701us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.310s 27.053us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.780s 33.539us 1 1 100.00
edn_csr_aliasing 1.380s 33.701us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.210s 113.468us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.210s 113.468us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.210s 113.468us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.250s 30.329us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.050s 160.620us 1 1 100.00
errs 1 1 100.00
edn_err 1.340s 20.582us 1 1 100.00
disable 2 2 100.00
edn_disable 0.910s 18.626us 1 1 100.00
edn_disable_auto_req_mode 1.100s 35.378us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.660s 563.941us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.040s 53.090us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.970s 40.834us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.560s 228.047us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.560s 228.047us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.880s 17.272us 1 1 100.00
edn_csr_rw 0.780s 33.539us 1 1 100.00
edn_csr_aliasing 1.380s 33.701us 1 1 100.00
edn_same_csr_outstanding 0.970s 71.515us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.880s 17.272us 1 1 100.00
edn_csr_rw 0.780s 33.539us 1 1 100.00
edn_csr_aliasing 1.380s 33.701us 1 1 100.00
edn_same_csr_outstanding 0.970s 71.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.110s 571.231us 1 1 100.00
edn_tl_intg_err 2.030s 114.282us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.840s 64.549us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.050s 160.620us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.110s 571.231us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.110s 571.231us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.110s 571.231us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.110s 571.231us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.050s 160.620us 1 1 100.00
edn_sec_cm 4.110s 571.231us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.050s 160.620us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.030s 114.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 56.830s 3595.192us 1 1 100.00