Simulation Results: hmac

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.44 %
  • code
  • 96.91 %
  • assert
  • 96.70 %
  • func
  • 44.71 %
  • line
  • 99.59 %
  • branch
  • 98.68 %
  • cond
  • 95.11 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.490s 4351.554us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.090s 39.183us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.670s 36.437us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.020s 219.040us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.900s 307.206us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.340s 57.797us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.670s 36.437us 1 1 100.00
hmac_csr_aliasing 2.900s 307.206us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 25.120s 598.797us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 36.990s 3611.842us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.100s 451.156us 1 1 100.00
hmac_test_sha384_vectors 22.550s 241.799us 1 1 100.00
hmac_test_sha512_vectors 412.270s 18653.900us 1 1 100.00
hmac_test_hmac256_vectors 8.550s 984.292us 1 1 100.00
hmac_test_hmac384_vectors 8.980s 586.283us 1 1 100.00
hmac_test_hmac512_vectors 11.140s 1273.397us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 14.150s 7245.731us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 477.750s 14222.693us 1 1 100.00
error 1 1 100.00
hmac_error 5.800s 1833.746us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 52.390s 7745.999us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.490s 4351.554us 1 1 100.00
hmac_long_msg 25.120s 598.797us 1 1 100.00
hmac_back_pressure 36.990s 3611.842us 1 1 100.00
hmac_datapath_stress 477.750s 14222.693us 1 1 100.00
hmac_burst_wr 14.150s 7245.731us 1 1 100.00
hmac_stress_all 123.280s 14130.431us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.490s 4351.554us 1 1 100.00
hmac_long_msg 25.120s 598.797us 1 1 100.00
hmac_back_pressure 36.990s 3611.842us 1 1 100.00
hmac_datapath_stress 477.750s 14222.693us 1 1 100.00
hmac_wipe_secret 52.390s 7745.999us 1 1 100.00
hmac_test_sha256_vectors 9.100s 451.156us 1 1 100.00
hmac_test_sha384_vectors 22.550s 241.799us 1 1 100.00
hmac_test_sha512_vectors 412.270s 18653.900us 1 1 100.00
hmac_test_hmac256_vectors 8.550s 984.292us 1 1 100.00
hmac_test_hmac384_vectors 8.980s 586.283us 1 1 100.00
hmac_test_hmac512_vectors 11.140s 1273.397us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.490s 4351.554us 1 1 100.00
hmac_long_msg 25.120s 598.797us 1 1 100.00
hmac_back_pressure 36.990s 3611.842us 1 1 100.00
hmac_datapath_stress 477.750s 14222.693us 1 1 100.00
hmac_burst_wr 14.150s 7245.731us 1 1 100.00
hmac_error 5.800s 1833.746us 1 1 100.00
hmac_wipe_secret 52.390s 7745.999us 1 1 100.00
hmac_test_sha256_vectors 9.100s 451.156us 1 1 100.00
hmac_test_sha384_vectors 22.550s 241.799us 1 1 100.00
hmac_test_sha512_vectors 412.270s 18653.900us 1 1 100.00
hmac_test_hmac256_vectors 8.550s 984.292us 1 1 100.00
hmac_test_hmac384_vectors 8.980s 586.283us 1 1 100.00
hmac_test_hmac512_vectors 11.140s 1273.397us 1 1 100.00
hmac_stress_all 123.280s 14130.431us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 123.280s 14130.431us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.600s 16.839us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.640s 31.185us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.850s 195.909us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.850s 195.909us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.090s 39.183us 1 1 100.00
hmac_csr_rw 0.670s 36.437us 1 1 100.00
hmac_csr_aliasing 2.900s 307.206us 1 1 100.00
hmac_same_csr_outstanding 2.000s 46.647us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.090s 39.183us 1 1 100.00
hmac_csr_rw 0.670s 36.437us 1 1 100.00
hmac_csr_aliasing 2.900s 307.206us 1 1 100.00
hmac_same_csr_outstanding 2.000s 46.647us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.170s 88.260us 1 1 100.00
hmac_tl_intg_err 3.710s 493.221us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.710s 493.221us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.490s 4351.554us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.370s 157.203us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 36.670s 5903.194us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.260s 100.416us 1 1 100.00