Simulation Results

Simulation Results: i2c

06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
87.25 %

code
82.05 %

assert
95.98 %

func
83.72 %

line
96.69 %

branch
92.83 %

cond
87.03 %

toggle
89.66 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		92.68%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	58.650s	7391.554us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	13.870s	3756.754us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.820s	42.950us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.780s	44.641us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.100s	790.487us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.160s	82.116us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.970s	83.671us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.780s	44.641us	1	1	100.00
	i2c_csr_aliasing	1.160s	82.116us	1	1	100.00

38/41 passed

92.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.990s	13.759us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	570.550s	138123.063us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	3.510s	878.851us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.760s	27.526us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	54.770s	32209.596us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	65.240s	5661.350us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.980s	65.758us	1	1	100.00
	i2c_host_fifo_fmt_empty	7.330s	439.787us	1	1	100.00
	i2c_host_fifo_reset_rx	1.980s	454.023us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	64.660s	8243.287us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	7.650s	4763.432us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.620s	112.959us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.140s	460.314us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	172.960s	20161.491us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.180s	2940.692us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	16.690s	1082.386us	1	1	100.00
	i2c_target_intr_smoke	5.180s	5083.821us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.470s	255.880us	1	1	100.00
	i2c_target_fifo_reset_tx	0.910s	844.165us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	15.750s	47511.260us	1	1	100.00
	i2c_target_stress_rd	16.690s	1082.386us	1	1	100.00
	i2c_target_intr_stress_wr	20.180s	14599.561us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.990s	1185.517us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	6.610s	3367.054us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.300s	5286.812us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.710s	1012.851us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.460s	1452.849us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.070s	454.959us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	3.510s	878.851us	1	1	100.00
	i2c_host_perf_precise	1.620s	52.591us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	7.650s	4763.432us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.130s	126.280us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	1.970s	510.225us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.970s	441.570us	1	1	100.00
	i2c_target_nack_txstretch	1.150s	342.950us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	6.770s	852.128us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.970s	517.592us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.810s	20.847us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.690s	40.364us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.700s	107.323us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.700s	107.323us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.820s	42.950us	1	1	100.00
	i2c_csr_rw	0.780s	44.641us	1	1	100.00
	i2c_csr_aliasing	1.160s	82.116us	1	1	100.00
	i2c_same_csr_outstanding	1.110s	28.673us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.820s	42.950us	1	1	100.00
	i2c_csr_rw	0.780s	44.641us	1	1	100.00
	i2c_csr_aliasing	1.160s	82.116us	1	1	100.00
	i2c_same_csr_outstanding	1.110s	28.673us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.330s	71.647us	1	1	100.00
	i2c_sec_cm	1.010s	116.877us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.330s	71.647us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	10.980s	2084.345us	1
target_error_intr				1
	i2c_target_unexp_stop	1.590s	246.081us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	4.980s	451.698us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	32383313710751623904075497606763873793208910449495166276044624729793524053863	80	UVM_INFO @ 13759349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	113841882029609843629244786209607795683190657049540474228720578385758518600929	89	UVM_INFO @ 451697822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	76978249484389485460906881114439748645348813940628878004735452288393919023412	84	UVM_INFO @ 460313660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	103181534332538553170934764467962017696050613147152748077914371769047400048872	78	UVM_INFO @ 246080598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	52372029093722875363915027543532293762355917568021887111444161159195624166852	94	UVM_INFO @ 2084345247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	114830473390319705318639488454932253769351828875922569368565168942395954186121	78	UVM_INFO @ 342949685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---