Simulation Results: kmac/unmasked

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.07 %
  • code
  • 89.93 %
  • assert
  • 97.90 %
  • func
  • 94.37 %
  • line
  • 97.52 %
  • branch
  • 95.68 %
  • cond
  • 94.55 %
  • toggle
  • 99.92 %
  • FSM
  • 61.98 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 9.710s 628.485us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.890s 19.801us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.900s 72.653us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 6.040s 633.167us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 4.150s 1194.562us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.770s 136.203us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.900s 72.653us 1 1 100.00
kmac_csr_aliasing 4.150s 1194.562us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.860s 15.881us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.420s 33.780us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1278.320s 243157.752us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 737.100s 164300.259us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1296.430s 173273.877us 1 1 100.00
kmac_test_vectors_sha3_256 1175.970s 16859.665us 1 1 100.00
kmac_test_vectors_sha3_384 22.530s 6726.084us 1 1 100.00
kmac_test_vectors_sha3_512 14.190s 3016.642us 1 1 100.00
kmac_test_vectors_shake_128 165.420s 95625.040us 1 1 100.00
kmac_test_vectors_shake_256 298.480s 154066.317us 1 1 100.00
kmac_test_vectors_kmac 2.100s 39.947us 1 1 100.00
kmac_test_vectors_kmac_xof 2.110s 333.101us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 41.130s 762.541us 1 1 100.00
app 1 1 100.00
kmac_app 255.440s 64530.457us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 52.170s 8344.184us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 197.360s 13023.019us 1 1 100.00
error 1 1 100.00
kmac_error 229.890s 62714.921us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 3.740s 3974.296us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 2.870s 444.527us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 28.980s 5439.624us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 8.660s 332.243us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 42.070s 16479.162us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 6.840s 1057.788us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 302.090s 5497.530us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.920s 14.014us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.910s 38.707us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.500s 86.657us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.500s 86.657us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.890s 19.801us 1 1 100.00
kmac_csr_rw 0.900s 72.653us 1 1 100.00
kmac_csr_aliasing 4.150s 1194.562us 1 1 100.00
kmac_same_csr_outstanding 2.560s 40.025us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.890s 19.801us 1 1 100.00
kmac_csr_rw 0.900s 72.653us 1 1 100.00
kmac_csr_aliasing 4.150s 1194.562us 1 1 100.00
kmac_same_csr_outstanding 2.560s 40.025us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.500s 45.299us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.500s 45.299us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.500s 45.299us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.500s 45.299us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.770s 61.069us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 29.080s 5913.860us 1 1 100.00
kmac_tl_intg_err 3.160s 145.481us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.160s 145.481us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 6.840s 1057.788us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 9.710s 628.485us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 41.130s 762.541us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.500s 45.299us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 29.080s 5913.860us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 29.080s 5913.860us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 29.080s 5913.860us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 9.710s 628.485us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 6.840s 1057.788us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 29.080s 5913.860us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 248.620s 58875.278us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 9.710s 628.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 35.770s 8256.730us 1 1 100.00