Simulation Results: lc_ctrl/volatile_unlock_disabled

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.58 %
  • code
  • 85.93 %
  • assert
  • 95.99 %
  • func
  • 92.81 %
  • line
  • 97.90 %
  • branch
  • 96.56 %
  • cond
  • 79.59 %
  • toggle
  • 90.15 %
  • FSM
  • 65.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.700s 149.686us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.930s 61.923us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.840s 49.456us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.210s 241.769us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.660s 52.746us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.830s 55.470us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.840s 49.456us 1 1 100.00
lc_ctrl_csr_aliasing 1.660s 52.746us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.270s 129.342us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.170s 1684.680us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.100s 31.356us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.680s 65.885us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.350s 811.466us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.010s 1411.135us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.350s 811.466us 1 1 100.00
lc_ctrl_prog_failure 1.680s 65.885us 1 1 100.00
lc_ctrl_errors 6.010s 1411.135us 1 1 100.00
lc_ctrl_security_escalation 8.270s 369.895us 1 1 100.00
lc_ctrl_jtag_state_failure 22.570s 9331.157us 1 1 100.00
lc_ctrl_jtag_prog_failure 19.050s 11870.616us 1 1 100.00
lc_ctrl_jtag_errors 49.710s 3101.492us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.020s 1123.120us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.800s 340.152us 1 1 100.00
lc_ctrl_jtag_prog_failure 19.050s 11870.616us 1 1 100.00
lc_ctrl_jtag_errors 49.710s 3101.492us 1 1 100.00
lc_ctrl_jtag_access 2.130s 93.647us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.180s 2309.153us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.700s 105.846us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.490s 360.579us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.500s 2283.025us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.740s 1193.006us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.040s 34.737us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.150s 473.886us 1 1 100.00
lc_ctrl_jtag_alert_test 1.110s 77.065us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.100s 2217.929us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.150s 108.967us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 52.050s 16357.819us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.200s 58.399us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.940s 190.455us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.940s 190.455us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.930s 61.923us 1 1 100.00
lc_ctrl_csr_rw 0.840s 49.456us 1 1 100.00
lc_ctrl_csr_aliasing 1.660s 52.746us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.220s 27.995us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.930s 61.923us 1 1 100.00
lc_ctrl_csr_rw 0.840s 49.456us 1 1 100.00
lc_ctrl_csr_aliasing 1.660s 52.746us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.220s 27.995us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.870s 180.455us 1 1 100.00
lc_ctrl_tl_intg_err 1.740s 365.898us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.740s 365.898us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.170s 1684.680us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.350s 811.466us 1 1 100.00
lc_ctrl_sec_cm 5.870s 180.455us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.350s 811.466us 1 1 100.00
lc_ctrl_sec_cm 5.870s 180.455us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.350s 811.466us 1 1 100.00
lc_ctrl_sec_cm 5.870s 180.455us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.350s 811.466us 1 1 100.00
lc_ctrl_sec_cm 5.870s 180.455us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.350s 811.466us 1 1 100.00
lc_ctrl_sec_cm 5.870s 180.455us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.350s 811.466us 1 1 100.00
lc_ctrl_sec_cm 5.870s 180.455us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.350s 811.466us 1 1 100.00
lc_ctrl_sec_cm 5.870s 180.455us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.350s 811.466us 1 1 100.00
lc_ctrl_sec_cm 5.870s 180.455us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.270s 369.895us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.270s 129.342us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.800s 340.152us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.720s 2058.243us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.720s 2058.243us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.080s 2189.714us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.140s 938.732us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.140s 938.732us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 24.000s 9981.753us 1 1 100.00