Simulation Results: lc_ctrl/volatile_unlock_enabled

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.07 %
  • code
  • 86.69 %
  • assert
  • 95.99 %
  • func
  • 93.53 %
  • line
  • 97.98 %
  • branch
  • 96.43 %
  • cond
  • 79.95 %
  • toggle
  • 90.01 %
  • FSM
  • 69.09 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 4.640s 168.082us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.820s 18.492us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.940s 128.493us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.480s 399.009us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 35.610us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.170s 24.490us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.940s 128.493us 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 35.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.590s 175.509us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.420s 899.809us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.980s 12.463us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.330s 82.062us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.330s 565.364us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.780s 733.073us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.330s 565.364us 1 1 100.00
lc_ctrl_prog_failure 1.330s 82.062us 1 1 100.00
lc_ctrl_errors 4.780s 733.073us 1 1 100.00
lc_ctrl_security_escalation 5.370s 659.087us 1 1 100.00
lc_ctrl_jtag_state_failure 24.320s 22640.903us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.110s 340.293us 1 1 100.00
lc_ctrl_jtag_errors 16.700s 1820.026us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.840s 1099.407us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.770s 326.153us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.110s 340.293us 1 1 100.00
lc_ctrl_jtag_errors 16.700s 1820.026us 1 1 100.00
lc_ctrl_jtag_access 5.610s 952.138us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.570s 1415.458us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.380s 497.910us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.680s 264.176us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.470s 3264.062us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.870s 2634.301us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.320s 30.139us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.770s 403.319us 1 1 100.00
lc_ctrl_jtag_alert_test 0.800s 21.921us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.170s 709.001us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.720s 23.244us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 314.020s 173443.598us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.100s 61.363us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.350s 450.824us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.350s 450.824us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.820s 18.492us 1 1 100.00
lc_ctrl_csr_rw 0.940s 128.493us 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 35.610us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.190s 115.288us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.820s 18.492us 1 1 100.00
lc_ctrl_csr_rw 0.940s 128.493us 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 35.610us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.190s 115.288us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.710s 454.722us 1 1 100.00
lc_ctrl_tl_intg_err 1.410s 468.185us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.410s 468.185us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.420s 899.809us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.330s 565.364us 1 1 100.00
lc_ctrl_sec_cm 5.710s 454.722us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.330s 565.364us 1 1 100.00
lc_ctrl_sec_cm 5.710s 454.722us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.330s 565.364us 1 1 100.00
lc_ctrl_sec_cm 5.710s 454.722us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.330s 565.364us 1 1 100.00
lc_ctrl_sec_cm 5.710s 454.722us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.330s 565.364us 1 1 100.00
lc_ctrl_sec_cm 5.710s 454.722us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.330s 565.364us 1 1 100.00
lc_ctrl_sec_cm 5.710s 454.722us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.330s 565.364us 1 1 100.00
lc_ctrl_sec_cm 5.710s 454.722us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.330s 565.364us 1 1 100.00
lc_ctrl_sec_cm 5.710s 454.722us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.370s 659.087us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.590s 175.509us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.770s 326.153us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.640s 461.047us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.640s 461.047us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 292.273us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.530s 736.567us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.530s 736.567us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 7.330s 694.866us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 92073069646456660967013688390287038506486881671709824676713048744182144862457 486
UVM_INFO @ 694865701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---