| V1 |
|
83.33% |
| V2 |
|
81.82% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 47.000s | 4896.670us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 56.573us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 1.000s | 49.826us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 3.000s | 263.973us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 1.000s | 80.765us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 1.000s | 7.539us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 1.000s | 49.826us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 80.765us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 1 | 1 | 100.00 | |||
| mbx_stress | 43.000s | 15213.503us | 1 | 1 | 100.00 | |
| mbx_max_activity | 1 | 1 | 100.00 | |||
| mbx_stress_zero_delays | 95.000s | 10836.757us | 1 | 1 | 100.00 | |
| mbx_imbx_oob | 0 | 1 | 0.00 | |||
| mbx_imbx_oob | 3.000s | 66.786us | 0 | 1 | 0.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 17.000s | 544.939us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 2.000s | 185.256us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 2.000s | 33.258us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 2.000s | 6.465us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| mbx_tl_errors | 2.000s | 6.465us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 56.573us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 49.826us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 80.765us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 35.393us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 56.573us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 49.826us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 1.000s | 80.765us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 35.393us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_tl_intg_err | 1.000s | 277.064us | 1 | 1 | 100.00 | |
| mbx_sec_cm | 1.000s | 34.396us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). | 2 test runs | |||
| mbx_tl_errors | 25590482609433654805632941407890651712890997702986743730450171415280667840449 | 85 |
TL item was: req: (cip_tl_seq_item@15484) { a_addr: 'hd77615f4 a_data: 'h838f67a4 a_mask: 'h9 a_size: 'h2 a_param: 'h0 a_source: 'h75 a_opcode: 'h1 a_user: 'h24fb4 d_param: 'h0 d_source: 'h75 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 6464606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| mbx_csr_mem_rw_with_rand_reset | 86108362433483728600980803801998444407232156969401847333724065241663707735081 | 92 |
TL item was: req: (cip_tl_seq_item@22816) { a_addr: 'h655a91b4 a_data: 'h7ffb929d a_mask: 'h3 a_size: 'h1 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h2756e d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 7539300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register | 1 test run | |||
| mbx_imbx_oob | 43717018809460973334598938349364589988854724388971157646658471204797641188314 | 94 |
UVM_INFO @ 66785788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|