Simulation Results: otp_ctrl

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.81 %
  • code
  • 71.06 %
  • assert
  • 93.60 %
  • func
  • 56.77 %
  • line
  • 87.55 %
  • branch
  • 83.94 %
  • cond
  • 85.88 %
  • toggle
  • 60.55 %
  • FSM
  • 37.40 %
Validation stages
V1
100.00%
V2
60.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.670s 139.306us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.950s 849.550us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.140s 236.509us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.980s 173.414us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.490s 254.309us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.240s 95.587us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.820s 241.655us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.980s 173.414us 1 1 100.00
otp_ctrl_csr_aliasing 4.240s 95.587us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.300s 162.121us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.330s 77.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 125.140s 80981.555us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.400s 153.639us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 8.260s 984.259us 0 1 0.00
otp_ctrl_check_fail 3.010s 86.599us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 2.860s 119.961us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 3.760s 637.961us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 51.290s 5411.268us 1 1 100.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 6.340s 647.127us 0 1 0.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 30.510s 5938.776us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 20.830s 2463.546us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 2.420s 995.840us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 4.100s 1683.297us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.460s 44.896us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.940s 243.644us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.820s 293.950us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.820s 293.950us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.140s 236.509us 1 1 100.00
otp_ctrl_csr_rw 1.980s 173.414us 1 1 100.00
otp_ctrl_csr_aliasing 4.240s 95.587us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.560s 194.850us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.140s 236.509us 1 1 100.00
otp_ctrl_csr_rw 1.980s 173.414us 1 1 100.00
otp_ctrl_csr_aliasing 4.240s 95.587us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.560s 194.850us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
otp_ctrl_tl_intg_err 22.390s 1619.326us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 22.390s 1619.326us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.950s 849.550us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.950s 849.550us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
otp_ctrl_macro_errs 20.830s 2463.546us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
otp_ctrl_macro_errs 20.830s 2463.546us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 14.990s 736.000us 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.400s 153.639us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.010s 86.599us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 3.760s 637.961us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 3.760s 637.961us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 3.760s 637.961us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 3.760s 637.961us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 3.760s 637.961us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.950s 849.550us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 3.760s 637.961us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.950s 849.550us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 283.410s 18841.452us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 2.860s 119.961us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.950s 849.550us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.950s 849.550us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 20.830s 2463.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 99.360s 46127.033us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 27.510s 3736.140us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 4 test runs
otp_ctrl_check_fail 112027491144816376368002573825714767385838245591503859823647210773871024973807 580
UVM_INFO @ 86599154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 111561720583499579278245692374293287039541114107049296721988728061924352563108 822
UVM_INFO @ 995840180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5161432130607336088006716455028971153528797676777232255803303016414225751521 12536
UVM_INFO @ 3736139699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 87810498846171524457147494513180856404514254750850192596178018572723135015480 543
UVM_INFO @ 1683297449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 112063853095864959524884073555844862329840523495042025147703637899998622285288 120593
UVM_INFO @ 80981554737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 27388039074662100001805681235922747481533992769420037117906038018128329993847 89
UVM_INFO @ 46127033165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_background_chks 6448501385868255880311787399385335951824178755563461432953794897786596608152 9288
UVM_INFO @ 984259097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_parallel_lc_req 84459312761002144076699015386511912012394426277300633594710886471567778343256 5180
UVM_INFO @ 647126997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_dai_lock 21043059549334452346146345179341107991113628117950176335012187623705050864808 2851
UVM_INFO @ 637961491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_regwen 42760711460686546405262457812907898423102986427264398216585209213208763602845 2062
UVM_INFO @ 119960813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---