Simulation Results: rom_ctrl/32kb

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.89 %
  • code
  • 99.51 %
  • assert
  • 96.80 %
  • func
  • 97.37 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.51 %
  • toggle
  • 99.44 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.850s 645.403us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.820s 175.388us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.050s 128.145us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.780s 312.542us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.240s 169.231us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.560s 181.188us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.050s 128.145us 1 1 100.00
rom_ctrl_csr_aliasing 4.240s 169.231us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.910s 289.692us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.300s 384.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.470s 432.487us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 15.650s 607.913us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.870s 1042.845us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.530s 129.201us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.140s 385.091us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.140s 385.091us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.820s 175.388us 1 1 100.00
rom_ctrl_csr_rw 4.050s 128.145us 1 1 100.00
rom_ctrl_csr_aliasing 4.240s 169.231us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.390s 546.115us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.820s 175.388us 1 1 100.00
rom_ctrl_csr_rw 4.050s 128.145us 1 1 100.00
rom_ctrl_csr_aliasing 4.240s 169.231us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.390s 546.115us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.160s 3266.235us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.370s 2207.047us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 195.510s 644.234us 1 1 100.00
rom_ctrl_tl_intg_err 23.760s 224.150us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 195.510s 644.234us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 195.510s 644.234us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.160s 3266.235us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.160s 3266.235us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.160s 3266.235us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.160s 3266.235us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.160s 3266.235us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 195.510s 644.234us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 195.510s 644.234us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.850s 645.403us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.850s 645.403us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.850s 645.403us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.760s 224.150us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.160s 3266.235us 1 1 100.00
rom_ctrl_kmac_err_chk 7.870s 1042.845us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.160s 3266.235us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.160s 3266.235us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 91.160s 3266.235us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.370s 2207.047us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 195.510s 644.234us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 385.200s 4188.710us 1 1 100.00