Simulation Results

Simulation Results: rv_dm/use_dmi_interface

06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
81.53 %

code
82.20 %

assert
96.09 %

func
66.29 %

line
93.58 %

branch
82.26 %

cond
81.34 %

toggle
72.59 %

FSM
81.25 %

Validation stages

V1		96.30%
V2		73.91%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	1.920s	1143.286us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	1.060s	245.236us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	1.180s	229.236us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	24.030s	10719.883us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	1.830s	1057.242us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	4.300s	4928.139us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	15.010s	6884.930us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	13.600s	6637.032us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	33.230s	43924.018us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	1.010s	246.876us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	1.050s	602.229us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	0.750s	159.269us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	0.920s	78.310us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	1.550s	597.879us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	1.870s	1035.870us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	0.730s	61.304us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	1.960s	1197.569us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	1.010s	246.876us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	0.860s	133.423us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	1.730s	526.993us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	0.750s	159.269us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	0.850s	61.320us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	1.490s	265.992us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	1.300s	69.139us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	38.210s	2919.472us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	51.790s	4321.242us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	1.670s	168.794us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	51.790s	4321.242us	1	1	100.00
	rv_dm_csr_rw	1.300s	69.139us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	0.750s	48.153us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	0.730s	31.671us	1	1	100.00

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	1.920s	1143.286us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	2.800s	996.343us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	0.940s	605.960us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	0.860s	614.247us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	3.600s	1546.292us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	3.330s	2655.649us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	0.730s	121.365us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	0.950s	140.399us	0	1	0.00
sba_autoincrement				1	1	100.00
	rv_dm_autoincr_sba_tl_access	5.550s	2437.659us	1	1	100.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	2.090s	655.184us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	9.510s	4985.108us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	1.350s	789.674us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	0.680s	37.214us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	11.700s	12978.043us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	73.060s	29193.850us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	0.790s	92.638us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	4991.170s	10000000.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	0.740s	96.874us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	4.450s	323.645us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	4.450s	323.645us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	51.790s	4321.242us	1	1	100.00
	rv_dm_csr_hw_reset	1.490s	265.992us	1	1	100.00
	rv_dm_csr_rw	1.300s	69.139us	1	1	100.00
	rv_dm_same_csr_outstanding	3.050s	208.053us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	51.790s	4321.242us	1	1	100.00
	rv_dm_csr_hw_reset	1.490s	265.992us	1	1	100.00
	rv_dm_csr_rw	1.300s	69.139us	1	1	100.00
	rv_dm_same_csr_outstanding	3.050s	208.053us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	1.280s	720.764us	1	1	100.00
	rv_dm_tl_intg_err	14.780s	3916.601us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	14.780s	3916.601us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	9.510s	4985.108us	1	1	100.00
	rv_dm_debug_disabled	0.860s	77.996us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	9.510s	4985.108us	1	1	100.00
	rv_dm_debug_disabled	0.860s	77.996us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	1.920s	1143.286us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	2.480s	597.577us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.840s	238.760us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	0.840s	238.760us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	2.480s	597.577us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	7.080s	483.929us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	565.310s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
Error-[CNST-CIF] Constraints inconsistency failure				2 test runs
	rv_dm_delayed_resp_sba_tl_access	68276510502969963452756587102137253008577160263763494843868871721969535328250	133	src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140 Constraints are inconsistent and cannot be solved. Please check the inconsistent constraints being printed above and rewrite them.
	rv_dm_bad_sba_tl_access	62055792222556168876909291286930263964866649815849998227443282072621903397943	133	src/lowrisc_dv_tl_agent_0/seq_lib/tl_device_seq.sv, 140 Constraints are inconsistent and cannot be solved. Please check the inconsistent constraints being printed above and rewrite them.
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	2241206308969832946058880764116674874198352745417894974709669593216694163005	77	UVM_INFO @ 655184308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	78240364268785672970836009652364385863609101424388776210641923654456121459059	85	UVM_INFO @ 483929084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	rv_dm_scanmode	108098326753717968581308158791698538305716254766309680119194931229855663406383	77	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	102467475360766491323456537135403852715939191235542598963932248658167682079710	82	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				1 test run
	rv_dm_sba_tl_access	62072659198540117696008134421641273567796101192204306699287673115832915096282	86	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @5290
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	87068578966554057491729365102970632736393037086391523573334794009589289586838	77	UVM_INFO @ 78309570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	48370397291216255502510039670027720881530259356347875051443249399484300252330	77	UVM_INFO @ 37213685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---