Simulation Results: rv_timer

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 96.47 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.050s 183.539us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.720s 15.489us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.850s 11.388us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.480s 38.410us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.950s 34.625us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.110s 23.263us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.850s 11.388us 1 1 100.00
rv_timer_csr_aliasing 0.950s 34.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.740s 165.856us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.440s 3367.975us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 2.590s 1961.897us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 2.590s 1961.897us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.550s 2736.007us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.550s 14.443us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.760s 24.031us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.340s 177.081us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.340s 177.081us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.720s 15.489us 1 1 100.00
rv_timer_csr_rw 0.850s 11.388us 1 1 100.00
rv_timer_csr_aliasing 0.950s 34.625us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 14.295us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.720s 15.489us 1 1 100.00
rv_timer_csr_rw 0.850s 11.388us 1 1 100.00
rv_timer_csr_aliasing 0.950s 34.625us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 14.295us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.740s 40.867us 1 1 100.00
rv_timer_tl_intg_err 0.830s 148.072us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.830s 148.072us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.660s 12.355us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 1.600s 221.277us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 23.680s 4547.174us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 18205810697106829625103521000134598005992402452391113405865151032462804905176 76
UVM_INFO @ 221277064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 23100974192038160083523996606755129360798374578858680377534292342098526838767 76
UVM_INFO @ 165856067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---