Simulation Results: sram_ctrl/main

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.94 %
  • code
  • 96.55 %
  • assert
  • 96.46 %
  • func
  • 94.80 %
  • block
  • 95.74 %
  • line
  • 96.44 %
  • branch
  • 93.68 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 369.453us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 65.108us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 31.952us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 340.321us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 11.978us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 351.976us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 31.952us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 11.978us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 107.000s 6980.823us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 103.000s 5222.168us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 23.000s 13969.494us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 102.000s 3676.233us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 113.000s 3085.382us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 47.000s 86135.132us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 36.000s 19085.497us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 30.000s 8083.320us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 727.047us 1 1 100.00
sram_ctrl_partial_access_b2b 242.000s 19414.787us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 2665.442us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 13352.722us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 992.959us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 725.668us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1460.665us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 138.000s 60956.902us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 15.154us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 70.880us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 70.880us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 65.108us 1 1 100.00
sram_ctrl_csr_rw 1.000s 31.952us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 11.978us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 21.455us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 65.108us 1 1 100.00
sram_ctrl_csr_rw 1.000s 31.952us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 11.978us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 21.455us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 3902.366us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1326.232us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 663.146us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1326.232us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 663.146us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 725.668us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 725.668us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 31.952us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 30.000s 8083.320us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 30.000s 8083.320us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 30.000s 8083.320us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 36.000s 19085.497us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2768.210us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 3902.366us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 6031.414us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 369.453us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 369.453us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 30.000s 8083.320us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1326.232us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 36.000s 19085.497us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1326.232us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1326.232us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 369.453us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1326.232us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 25.000s 1189.123us 1 1 100.00