Simulation Results: uart

 
06/05/2026 19:39:25 DVSim: v1.34.0 sha: 96721aa json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.88 %
  • code
  • 95.87 %
  • assert
  • 97.12 %
  • func
  • 64.66 %
  • line
  • 99.17 %
  • branch
  • 96.97 %
  • cond
  • 95.80 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.270s 981.153us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.630s 13.354us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.630s 33.317us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.820s 222.507us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.840s 18.358us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.850s 21.143us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.630s 33.317us 1 1 100.00
uart_csr_aliasing 0.840s 18.358us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 20.930s 224918.899us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.270s 981.153us 1 1 100.00
uart_tx_rx 20.930s 224918.899us 1 1 100.00
parity_error 2 2 100.00
uart_intr 8.720s 14044.356us 1 1 100.00
uart_rx_parity_err 58.350s 38023.690us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 20.930s 224918.899us 1 1 100.00
uart_intr 8.720s 14044.356us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 31.700s 26866.766us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 21.800s 38424.162us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 8.310s 12926.539us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 8.720s 14044.356us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 8.720s 14044.356us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 8.720s 14044.356us 1 1 100.00
perf 1 1 100.00
uart_perf 301.900s 13115.360us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.250s 8026.415us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.250s 8026.415us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.220s 1861.263us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.150s 5112.578us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 9.750s 13571.125us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 16.190s 2762.107us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 462.130s 133295.477us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 354.740s 201522.529us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.820s 53.703us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.670s 36.112us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.380s 237.304us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.380s 237.304us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.630s 13.354us 1 1 100.00
uart_csr_rw 0.630s 33.317us 1 1 100.00
uart_csr_aliasing 0.840s 18.358us 1 1 100.00
uart_same_csr_outstanding 0.850s 27.382us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.630s 13.354us 1 1 100.00
uart_csr_rw 0.630s 33.317us 1 1 100.00
uart_csr_aliasing 0.840s 18.358us 1 1 100.00
uart_same_csr_outstanding 0.850s 27.382us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.900s 37.758us 1 1 100.00
uart_tl_intg_err 0.910s 185.724us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.910s 185.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 26.890s 3031.104us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 14932346794532705496448620147694662377847703149042054297483345676830248396460 74
UVM_ERROR @ 357042544 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 357079581 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1189078749 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 1189078749 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0