Simulation Results: ac_range_check

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.80 %
  • code
  • 92.76 %
  • assert
  • 97.75 %
  • func
  • 57.88 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.11 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 28.000s 2352.460us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 41.000s 7461.177us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 33.659us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 177.849us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 21.000s 1013.918us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 14.000s 1426.609us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 148.064us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 177.849us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 1426.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 51.723us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 22.000s 472.170us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 206.000s 8685.340us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 26.754us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 60.561us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 429.822us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 429.822us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 33.659us 1 1 100.00
ac_range_check_csr_rw 3.000s 177.849us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 1426.609us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 278.732us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 33.659us 1 1 100.00
ac_range_check_csr_rw 3.000s 177.849us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 1426.609us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 278.732us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 2348.748us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 2348.748us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 2348.748us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 2348.748us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 83.000s 4991.677us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 67.836us 1 1 100.00
ac_range_check_tl_intg_err 10.000s 1622.550us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 383.000s 6698.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 29.000s 9289.648us 1 1 100.00