Simulation Results: aes/gcm_masked

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.35 %
  • code
  • 95.23 %
  • assert
  • 98.29 %
  • func
  • 68.52 %
  • block
  • 95.88 %
  • line
  • 97.56 %
  • branch
  • 89.84 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 82.575us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 148.378us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 194.989us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 93.513us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 526.827us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 581.307us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 293.268us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 93.513us 1 1 100.00
aes_csr_aliasing 3.000s 581.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 148.378us 1 1 100.00
aes_config_error 4.000s 283.445us 1 1 100.00
aes_stress 4.000s 138.825us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 148.378us 1 1 100.00
aes_config_error 4.000s 283.445us 1 1 100.00
aes_stress 4.000s 138.825us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 138.825us 1 1 100.00
aes_b2b 23.000s 354.063us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 138.825us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 148.378us 1 1 100.00
aes_config_error 4.000s 283.445us 1 1 100.00
aes_stress 4.000s 138.825us 1 1 100.00
aes_alert_reset 9.000s 754.546us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 108.206us 1 1 100.00
aes_config_error 4.000s 283.445us 1 1 100.00
aes_alert_reset 9.000s 754.546us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 122.518us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 348.093us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 1187.903us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 9.000s 754.546us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 138.825us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 138.825us 1 1 100.00
aes_sideload 3.000s 162.909us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 400.001us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 13.000s 301.552us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 70.597us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 85.662us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 138.033us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 138.033us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 194.989us 1 1 100.00
aes_csr_rw 1.000s 93.513us 1 1 100.00
aes_csr_aliasing 3.000s 581.307us 1 1 100.00
aes_same_csr_outstanding 2.000s 121.131us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 194.989us 1 1 100.00
aes_csr_rw 1.000s 93.513us 1 1 100.00
aes_csr_aliasing 3.000s 581.307us 1 1 100.00
aes_same_csr_outstanding 2.000s 121.131us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 6.000s 265.321us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 22.000s 10020.724us 0 1 0.00
aes_control_fi 1.000s 47.209us 1 1 100.00
aes_cipher_fi 2.000s 71.445us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 123.214us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 123.214us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 123.214us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 123.214us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 135.626us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 987.041us 1 1 100.00
aes_tl_intg_err 2.000s 139.745us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 139.745us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 9.000s 754.546us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 123.214us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 123.214us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 148.378us 1 1 100.00
aes_stress 4.000s 138.825us 1 1 100.00
aes_alert_reset 9.000s 754.546us 1 1 100.00
aes_core_fi 3.000s 80.439us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 70.597us 1 1 100.00
aes_config_error 4.000s 283.445us 1 1 100.00
aes_stress 4.000s 138.825us 1 1 100.00
aes_core_fi 3.000s 80.439us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 123.214us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 90.933us 1 1 100.00
aes_stress 4.000s 138.825us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 138.825us 1 1 100.00
aes_sideload 3.000s 162.909us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 90.933us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 90.933us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 90.933us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 90.933us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 90.933us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 138.825us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 138.825us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 22.000s 10020.724us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 22.000s 10020.724us 0 1 0.00
aes_control_fi 1.000s 47.209us 1 1 100.00
aes_cipher_fi 2.000s 71.445us 1 1 100.00
aes_ctr_fi 2.000s 60.947us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 22.000s 10020.724us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 22.000s 10020.724us 0 1 0.00
aes_control_fi 1.000s 47.209us 1 1 100.00
aes_cipher_fi 2.000s 71.445us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 71.445us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 22.000s 10020.724us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 22.000s 10020.724us 0 1 0.00
aes_control_fi 1.000s 47.209us 1 1 100.00
aes_ctr_fi 2.000s 60.947us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 22.000s 10020.724us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 22.000s 10020.724us 0 1 0.00
aes_control_fi 1.000s 47.209us 1 1 100.00
aes_cipher_fi 2.000s 71.445us 1 1 100.00
aes_ctr_fi 2.000s 60.947us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 9.000s 754.546us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 22.000s 10020.724us 0 1 0.00
aes_control_fi 1.000s 47.209us 1 1 100.00
aes_cipher_fi 2.000s 71.445us 1 1 100.00
aes_ctr_fi 2.000s 60.947us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 22.000s 10020.724us 0 1 0.00
aes_control_fi 1.000s 47.209us 1 1 100.00
aes_cipher_fi 2.000s 71.445us 1 1 100.00
aes_ctr_fi 2.000s 60.947us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 22.000s 10020.724us 0 1 0.00
aes_control_fi 1.000s 47.209us 1 1 100.00
aes_ctr_fi 2.000s 60.947us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 2.000s 71.989us 1 1 100.00
aes_fi 22.000s 10020.724us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 22.000s 10020.724us 0 1 0.00
aes_control_fi 1.000s 47.209us 1 1 100.00
aes_cipher_fi 2.000s 71.445us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 15.000s 745.211us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred! 1 test run
aes_fi 24943276271191721888055148239941941828762683107403585236040725337091193272649 1713
UVM_INFO @ 10020723604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 58182377802713326253242124213152411551839547745800293019842058125073335425071 683
UVM_INFO @ 745210922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---