Simulation Results: aes/gcm_unmasked

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.58 %
  • code
  • 90.89 %
  • assert
  • 97.75 %
  • func
  • 65.11 %
  • block
  • 90.41 %
  • line
  • 92.38 %
  • branch
  • 82.42 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 61.750us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 102.137us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 81.772us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 79.365us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 618.062us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 114.572us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 115.353us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 79.365us 1 1 100.00
aes_csr_aliasing 2.000s 114.572us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 102.137us 1 1 100.00
aes_config_error 3.000s 68.168us 1 1 100.00
aes_stress 2.000s 104.171us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 102.137us 1 1 100.00
aes_config_error 3.000s 68.168us 1 1 100.00
aes_stress 2.000s 104.171us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 104.171us 1 1 100.00
aes_b2b 2.000s 76.064us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 104.171us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 102.137us 1 1 100.00
aes_config_error 3.000s 68.168us 1 1 100.00
aes_stress 2.000s 104.171us 1 1 100.00
aes_alert_reset 12.000s 10060.469us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 57.051us 1 1 100.00
aes_config_error 3.000s 68.168us 1 1 100.00
aes_alert_reset 12.000s 10060.469us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 71.784us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 181.842us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 12.000s 10060.469us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 104.171us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 104.171us 1 1 100.00
aes_sideload 2.000s 73.355us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 130.560us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 5.000s 1069.674us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 69.833us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 93.548us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 93.548us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 81.772us 1 1 100.00
aes_csr_rw 1.000s 79.365us 1 1 100.00
aes_csr_aliasing 2.000s 114.572us 1 1 100.00
aes_same_csr_outstanding 2.000s 60.384us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 81.772us 1 1 100.00
aes_csr_rw 1.000s 79.365us 1 1 100.00
aes_csr_aliasing 2.000s 114.572us 1 1 100.00
aes_same_csr_outstanding 2.000s 60.384us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 102.970us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 13.000s 10019.992us 0 1 0.00
aes_control_fi 1.000s 53.883us 1 1 100.00
aes_cipher_fi 2.000s 47.084us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 149.468us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 149.468us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 149.468us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 149.468us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 615.769us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 993.351us 1 1 100.00
aes_tl_intg_err 3.000s 478.463us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 478.463us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 12.000s 10060.469us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 149.468us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 149.468us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 102.137us 1 1 100.00
aes_stress 2.000s 104.171us 1 1 100.00
aes_alert_reset 12.000s 10060.469us 0 1 0.00
aes_core_fi 3.000s 97.551us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 68.168us 1 1 100.00
aes_stress 2.000s 104.171us 1 1 100.00
aes_core_fi 3.000s 97.551us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 149.468us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 111.973us 1 1 100.00
aes_stress 2.000s 104.171us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 104.171us 1 1 100.00
aes_sideload 2.000s 73.355us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 111.973us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 111.973us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 111.973us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 111.973us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 111.973us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 104.171us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 104.171us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 13.000s 10019.992us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 13.000s 10019.992us 0 1 0.00
aes_control_fi 1.000s 53.883us 1 1 100.00
aes_cipher_fi 2.000s 47.084us 1 1 100.00
aes_ctr_fi 2.000s 63.288us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 13.000s 10019.992us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 13.000s 10019.992us 0 1 0.00
aes_control_fi 1.000s 53.883us 1 1 100.00
aes_cipher_fi 2.000s 47.084us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 47.084us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 13.000s 10019.992us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 13.000s 10019.992us 0 1 0.00
aes_control_fi 1.000s 53.883us 1 1 100.00
aes_ctr_fi 2.000s 63.288us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 13.000s 10019.992us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 13.000s 10019.992us 0 1 0.00
aes_control_fi 1.000s 53.883us 1 1 100.00
aes_cipher_fi 2.000s 47.084us 1 1 100.00
aes_ctr_fi 2.000s 63.288us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 12.000s 10060.469us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 13.000s 10019.992us 0 1 0.00
aes_control_fi 1.000s 53.883us 1 1 100.00
aes_cipher_fi 2.000s 47.084us 1 1 100.00
aes_ctr_fi 2.000s 63.288us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 13.000s 10019.992us 0 1 0.00
aes_control_fi 1.000s 53.883us 1 1 100.00
aes_cipher_fi 2.000s 47.084us 1 1 100.00
aes_ctr_fi 2.000s 63.288us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 13.000s 10019.992us 0 1 0.00
aes_control_fi 1.000s 53.883us 1 1 100.00
aes_ctr_fi 2.000s 63.288us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 13.000s 10019.992us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 13.000s 10019.992us 0 1 0.00
aes_control_fi 1.000s 53.883us 1 1 100.00
aes_cipher_fi 2.000s 47.084us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 10.000s 1283.731us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred! 1 test run
aes_alert_reset 106210684541105237456986797019599193515287272683056517381741354000555543295415 1295
UVM_INFO @ 10060469397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred! 1 test run
aes_fi 108486757204773878551135291903217270074073042747548624331644398663786388722751 1100
UVM_INFO @ 10019991553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 87638809738674382054096317106203899441680971994215234272364089004785138301578 225
UVM_INFO @ 1283730880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---