Simulation Results: alert_handler

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.76 %
  • code
  • 92.87 %
  • assert
  • 98.38 %
  • func
  • 81.03 %
  • line
  • 99.73 %
  • branch
  • 98.14 %
  • cond
  • 91.78 %
  • toggle
  • 94.03 %
  • FSM
  • 80.65 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 56.870s 2633.795us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.670s 60.560us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 8.130s 136.402us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 308.110s 49765.983us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 107.410s 9082.870us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.640s 68.464us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 8.130s 136.402us 1 1 100.00
alert_handler_csr_aliasing 107.410s 9082.870us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 162.730s 4060.838us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 10.130s 568.882us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1227.220s 112314.650us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 30.080s 2864.084us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 56.870s 2633.795us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 5.370s 342.457us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 21.870s 2315.479us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 13.610s 1713.465us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 2531.870s 370375.408us 1 1 100.00
alert_handler_lpg_stub_clk 2006.820s 104865.462us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1102.730s 26304.405us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 19.610s 2298.472us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.180s 48.009us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.410s 11.241us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 8.240s 781.928us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 8.240s 781.928us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.670s 60.560us 1 1 100.00
alert_handler_csr_rw 8.130s 136.402us 1 1 100.00
alert_handler_csr_aliasing 107.410s 9082.870us 1 1 100.00
alert_handler_same_csr_outstanding 23.420s 203.280us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.670s 60.560us 1 1 100.00
alert_handler_csr_rw 8.130s 136.402us 1 1 100.00
alert_handler_csr_aliasing 107.410s 9082.870us 1 1 100.00
alert_handler_same_csr_outstanding 23.420s 203.280us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 67.100s 1626.871us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 67.100s 1626.871us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 67.100s 1626.871us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 67.100s 1626.871us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 917.820s 70359.958us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 18.640s 828.574us 1 1 100.00
alert_handler_tl_intg_err 36.110s 987.252us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 36.110s 987.252us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 67.100s 1626.871us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 56.870s 2633.795us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 56.870s 2633.795us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 56.870s 2633.795us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 56.870s 2633.795us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 30.080s 2864.084us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2531.870s 370375.408us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 30.080s 2864.084us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1227.220s 112314.650us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1227.220s 112314.650us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 18.640s 828.574us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 18.640s 828.574us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 18.640s 828.574us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 18.640s 828.574us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 18.640s 828.574us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.640s 828.574us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.640s 828.574us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.640s 828.574us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 18.640s 828.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 439.160s 5902.553us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. 1 test run
alert_handler_ping_timeout 13929622731680820536918842973299312678100310031612713751629594000864840392045 80
UVM_INFO @ 1713465382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---