Simulation Results: clkmgr

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.98 %
  • code
  • 69.77 %
  • assert
  • 90.08 %
  • func
  • 59.08 %
  • line
  • 82.32 %
  • branch
  • 87.53 %
  • cond
  • 79.19 %
  • toggle
  • 99.81 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.180s 54.134us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.080s 23.002us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.690s 2.992us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.690s 11.953us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 2.120s 191.418us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.060s 9.715us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.690s 2.992us 0 1 0.00
clkmgr_csr_aliasing 2.120s 191.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.190s 41.513us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.200s 26.353us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.190s 78.930us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.180s 54.134us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.700s 6.654us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.600s 5.097us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.700s 6.654us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.780s 91.337us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.440s 53.276us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.550s 307.223us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.550s 307.223us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.080s 23.002us 1 1 100.00
clkmgr_csr_rw 0.690s 2.992us 0 1 0.00
clkmgr_csr_aliasing 2.120s 191.418us 1 1 100.00
clkmgr_same_csr_outstanding 0.860s 3.949us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.080s 23.002us 1 1 100.00
clkmgr_csr_rw 0.690s 2.992us 0 1 0.00
clkmgr_csr_aliasing 2.120s 191.418us 1 1 100.00
clkmgr_same_csr_outstanding 0.860s 3.949us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 6.330s 651.066us 1 1 100.00
clkmgr_tl_intg_err 0.810s 8.521us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 47.092us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 47.092us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 47.092us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 47.092us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.640s 5.318us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.810s 8.521us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.700s 6.654us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.600s 5.097us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.100s 47.092us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.480s 99.472us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.690s 2.992us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 6.330s 651.066us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.690s 2.992us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.690s 2.992us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 6.330s 651.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.720s 2.205us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.990s 27.550us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 75666193975326115041018490530269315598875213952416302709813547691402100734185 76
UVM_INFO @ 6653923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 72263439605426167258000951456326680145079909912932667649947755285239005957075 77
UVM_INFO @ 27550159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 1333317958042044185862102296136206794292230390484516892090392171468633985053 78
UVM_INFO @ 5096730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 43529210621672691223097118604618927842768826112036261576945819644221136407426 78
UVM_INFO @ 91336987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 55692381983362301378282559223195555926184782122945620042257210497319416055632 75
UVM_INFO @ 5318016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 93510097662680791606701638948975126842331576368840521909767601164002023447214 76
UVM_INFO @ 9715157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_tl_intg_err 44216794324294126309414083652135225560774591127200023994151177848673098213277 78
UVM_INFO @ 8521185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 33480131156709040730538835623311263868417917459802327969705630538292127290686 75
UVM_INFO @ 2991816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 102486122263788906947237150712514852541860350974842215058629822012301616669082 74
UVM_INFO @ 2205050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 44526918195571609249763253903361026797989811531198802849068175485940530762152 75
UVM_INFO @ 11952540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 60426447993977368579276657883728146059534368029389042008973638294379469440537 75
UVM_INFO @ 3948973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---