Simulation Results: csrng

 
07/05/2026 19:40:22 DVSim: v1.34.0 sha: 2ee0202 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.49 %
  • code
  • 92.33 %
  • assert
  • 93.23 %
  • func
  • 76.91 %
  • block
  • 96.98 %
  • line
  • 97.80 %
  • branch
  • 92.42 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 39.726us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 19.522us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 19.662us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 4.000s 87.436us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 30.952us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 67.148us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 19.662us 1 1 100.00
csrng_csr_aliasing 2.000s 30.952us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
alerts 1 1 100.00
csrng_alert 10.000s 529.636us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 4.000s 245.148us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 4.000s 245.148us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 264.000s 14167.426us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 27.425us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 62.956us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 126.399us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 126.399us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 19.522us 1 1 100.00
csrng_csr_rw 2.000s 19.662us 1 1 100.00
csrng_csr_aliasing 2.000s 30.952us 1 1 100.00
csrng_same_csr_outstanding 2.000s 33.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 19.522us 1 1 100.00
csrng_csr_rw 2.000s 19.662us 1 1 100.00
csrng_csr_aliasing 2.000s 30.952us 1 1 100.00
csrng_same_csr_outstanding 2.000s 33.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 252.325us 1 1 100.00
csrng_tl_intg_err 7.000s 269.389us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 15.770us 1 1 100.00
csrng_csr_rw 2.000s 19.662us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 10.000s 529.636us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 264.000s 14167.426us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
csrng_sec_cm 4.000s 252.325us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
csrng_sec_cm 4.000s 252.325us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
csrng_sec_cm 4.000s 252.325us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
csrng_sec_cm 4.000s 252.325us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
csrng_sec_cm 4.000s 252.325us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 10.000s 529.636us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 264.000s 14167.426us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 10.000s 529.636us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 7.000s 269.389us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
csrng_sec_cm 4.000s 252.325us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
csrng_sec_cm 4.000s 252.325us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 46.964us 1 1 100.00
csrng_err 2.000s 19.185us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 10802.950s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 19195243513949078585535525539332229500983413002343998484082706036873825272374 130
UVM_INFO @ 245147774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 10052969041681782947164725814416034492440617539314398327727153578817422839982 None